`timescale 1ns/100ps
module jmem16x1024 (clk,addr,din,dout,we);
parameter AWIDTH=10, DWIDTH=16;
input			clk, we;
input	[AWIDTH -1:0]	addr;
input	[DWIDTH -1:0]	din;
output	[DWIDTH -1:0]	dout;
jmjsram #(AWIDTH,DWIDTH,"mem0.hex") Mem0 (clk, addr, din, dout, we);
jmjsram #(AWIDTH,DWIDTH) Mem1 (clk, addr, din, dout, we);
endmodule
//----------------------------------------------------------------------------//
module jmjsram (clk, addr, din, dout, we);
//----------------------------------------------------------------------------//
parameter AWIDTH=2, DWIDTH=2, INIT_FILE="";
input			clk, we;
input	[AWIDTH -1:0]	addr;
input	[DWIDTH -1:0]	din;
output	[DWIDTH -1:0]	dout;
//------------------------------------//
reg	[AWIDTH -1:0]	addr_r;
reg	[DWIDTH -1:0]	mem[0:(1<<AWIDTH)-1];

initial	if(INIT_FILE) $readmemh(INIT_FILE,mem);

always @(posedge clk) begin
	if(we) mem[addr] <= din;
	addr_r <= addr;
end
//------------------------------------//
assign dout = mem[addr_r];
//------------------------------------//
endmodule
//----------------------------------------------------------------------------//