`timescale 1 ns / 100 ps

module abc ();
reg clk;
reg [3:0] count;

initial clk=0;
always #10 clk=~clk;

initial count=0;
always @ (posedge clk) count<=count+1;

always @ (negedge clk) $strobe("count=%d",count);

initial begin
	$dumpfile("abc.vcd");
	$dumpvars;
	#1000
	$finish;
end

endmodule