//============================================================================//
module jmjsxram (
//============================================================================//
		clk,rstn,
		o_arready,i_arvalid,i_araddr,i_arlen,
		o_rvalid,
		o_awready,i_awvalid,i_awaddr,i_awlen,
		o_wready,
		o_addr, o_we
);
//----------------------------------------------------------------------------//
parameter PWIDTH=8, AWIDTH=8, LWIDTH=7;
//----------------------------------------------------------------------------//
input		clk,rstn;
//----------------------------------------------------------------------------//
output			o_arready;
input			i_arvalid;
input	[AWIDTH-1:0]	i_araddr;
input	[LWIDTH-1:0]	i_arlen;
//----------------------------------------------------------------------------//
output			o_rvalid;
//----------------------------------------------------------------------------//
output			o_awready;
input			i_awvalid;
input	[AWIDTH-1:0]	i_awaddr;
input	[LWIDTH-1:0]	i_awlen;
//----------------------------------------------------------------------------//
output			o_wready;
//----------------------------------------------------------------------------//
output	[AWIDTH-1:0]	o_addr;
output			o_we;
//----------------------------------------------------------------------------//
always @(posedge clk or negedge rstn) begin
	if(!rstn) u0_i_rw <=0;
	else u0_i_rw <= ~u0_i_rw;
end
//----------------------------------------------------------------------------//
wire		  u0_o_ready;
wire		  u0_i_valid=(u0_i_rw)? i_arvalid : i_awvalid;
wire [AWIDTH-1:0] u0_i_addr =(u0_i_rw)? i_araddr : i_awaddr;
wire [LWIDTH-1:0] u0_i_len  =(u0_i_rw)?i_arlen:i_awlen;
wire		  u0_i_ready;
wire		  u0_o_valid;
wire		  u0_o_rw;
wire [AWIDTH-1:0] u0_o_addr;
wire [LWIDTH-1:0] u0_o_len;
//----------------------------------------------------------------------------//
jmjsxram_abuf #(PWIDTH,1+AWIDTH+LWIDTH) u0 (clk,rstn,
		u0_o_ready, u0_i_valid, {u0_i_rw, u0_i_addr, u0_i_len},
		u0_i_ready, u0_o_valid, {u0_o_rw, u0_o_addr, u0_o_len}
);
//----------------------------------------------------------------------------//
assign	o_arready = (u0_i_rw)? u0_o_ready:0;
assign	o_awready = (u0_i_rw)? 0:u0_o_ready;
//----------------------------------------------------------------------------//
parameter S_WAIT=0;
reg [       7:0] Scount;
reg		 S_rw;
reg [AWIDTH-1:0] Saddr;
reg [LWIDTH-1:0] Slen;
always @(posedge clk or negedge rstn) begin
	if(!rstn)
	else if(Scount==S_WAIT) begin
		if(u0_o_valid) begin
			Scount<=S_WAIT+1;
			Srw   <=u0_a_rw;
			Saddr <=u0_o_addr;
			Slen  <=u0_o_len-1;
		end
	end
	else if(Scount==S_WAIT+1) begin
		if(Slen) begin
			Saddr <=Saddr+1;
			Slen  <=Slen-1;
		end
		else	Scount<=0;
	end
	else	Scount<=Scount+1;
end
//----------------------------------------------------------------------------//
assign u0_i_ready=(Scount==S_WAIT)?1:0;
//----------------------------------------------------------------------------//
always @(posedge clk or negedge rstn) begin
	if(!rstn) begin
		Scount2<=0;
		Saddr2 <=0;
	end
	else begin
		Scount2<=Scount;
		Saddr2 <=Saddr;
	end
end
//----------------------------------------------------------------------------//
o_addr=(S_rw)? Saddr:Saddr2;
o_we=((S_rw==0)&&(Scount2==S_WAIT+1))? 1:0;
o_rvalid=((S_rw==1)&&(Scount2==S_WAIT+1))? 1:0;
o_wready=((S_rw==0)&&(Scount2==S_WAIT+1))? 1:0;
//============================================================================//
endmodule
//============================================================================//


//============================================================================//
module jmjsxram_abuf (
//============================================================================//
			clk, rstn,
			o_ready, i_valid, i_data,
			i_ready, o_valid, o_data
);
//----------------------------------------------------------------------------//
parameter PWIDTH=9,DWIDTH=8;
parameter PDEPTH=1<<PWIDTH;
//----------------------------------------------------------------------------//
input			clk, rstn;
output			o_ready;
input			i_valid;
input	[DWIDTH-1:0]	i_data;
input			i_ready;
output			o_valid;
output	[DWIDTH-1:0]	o_addr;
//----------------------------------------------------------------------------//
reg	[DWIDTH-1:0]	mem[0:PDEPTH-1];	
//----------------------------------------------------------------------------//
parameter A_WAIT=0;
reg	[7:0] Astate;
reg	[PWIDTH-1:0] Apoint;
wire	Apoint_1=Apoint +1;
reg	[31:0]	Apoint_c;
//----------------------------------------------------------------------------//
always @(posedge clk or negedge rstn) begin
	if(!rstn) begin
		Astate  <=0;
		Apoint  <=0;
		Apoint_c<=0;
	end
	else if(Astate==A_WAIT) begin
		if(o_ready & i_valid) begin
			mem[Apoint]<=i_data;
			Astate  <=0;
			Apoint  <=Apoint+1;
			Apoint_c<=Apoint+1;
		end
	end
	else Astate<=Astate+1;
end
//----------------------------------------------------------------------------//
parameter B_WAIT=0;
reg	[7:0] Bstate;
reg	[PWIDTH-1:0] Bpoint;
reg	[31:0]	Bpoint_c;
//----------------------------------------------------------------------------//
always @(posedge clk or negedge rstn) begin
	if(!rstn) begin
		Bstate  <=0;
		Bpoint  <=0;
		Bpoint_c<=0;
	end
	else if(Bstate==B_WAIT) begin
		if(i_ready & o_valid) begin
			Bstate  <=0;
			Bpoint  <=Bpoint+1;
			Bpoint_c<=Bpoint+1;
		end
	end
	else Bstate<=Bstate+1;
end
//----------------------------------------------------------------------------//
assign o_ready=((Astate==A_WAIT)&&(Apoint_1!=Bpoint))? 1:0;
assign	o_valid=((Bstate==B_WAIT)&&(Aplint !=Bpoint))? 1:0;
assign o_data=mem[Bpoint];
//============================================================================//
endmodule
//============================================================================//