library ieee;
use ieee.std_logic_1164.all;

entity KawiBawiBo_tb is

end KawiBawiBo_tb;

architecture JMJS_Logic of KawiBawiBo_tb is
    signal A_S, A_R, A_P : std_logic;
    signal B_S, B_R, B_P : std_logic;
    signal Winner        : std_logic_vector(1 downto 0);

    component KawiBawiBo 
        port(A_S, A_R, A_P : in std_logic;
	     B_S, B_R, B_P : in std_logic;
	     Winner        : out std_logic_vector(1 downto 0));
    end component;
begin

    U0 : KawiBawiBo port map(A_S, A_R, A_P, B_S, B_R, B_P, Winner);

    process
    begin
	A_S <= '0'; A_R <= '0'; A_P <= '0';
	B_S <= '0'; B_R <= '0'; B_P <= '0';
	wait for 20 ns;
        A_R <= '1'; B_R <= '1';
	wait for 20 ns;
	A_R <= '0'; B_R <= '0';
	wait for 20 ns;
	A_S <= '1'; B_R <= '1';	 
	wait for 20 ns;
	A_S <= '0'; B_R <= '0';
	wait for 20 ns;
	A_P <= '1'; B_S <= '1';
	wait for 20 ns;
	A_P <= '0'; B_S <= '0';
	wait for 20 ns;
	A_R <= '1';
	wait for 20 ns;
	A_R <= '0';
	wait for 20 ns;
	A_S <= '1'; B_P <= '1';
	wait for 20 ns;
	A_S <= '0'; B_P <= '0';
	wait for 20 ns;
	A_P <= '1'; B_P <= '1';
	wait for 20 ns;
	A_P <= '0'; B_P <= '0';
	wait for 20 ns;
	A_R <= '1'; B_S <= '1';
	wait for 20 ns;
	A_R <= '0'; B_S <= '0';
	wait for 20 ns;
	
    end process;

end JMJS_Logic;