library ieee; use ieee.std_logic_1164.all; entity comparator_tb is end comparator_tb; architecture JMJS_Logic of comparator_tb is signal A, B : std_logic_vector(3 downto 0); signal Result : std_logic_vector(1 downto 0); component comparator port(A, B : in std_logic_vector(3 downto 0); Result : out std_logic_vector(1 downto 0)); end component; begin U0 : comparator port map(A, B, Result); process begin A <= "0011"; B <= "0101"; wait for 20 ns; A <= "1000"; wait for 20 ns; B <= "1100"; wait for 20 ns; A <= "0110"; wait for 20 ns; B <= "1011"; wait for 20 ns; A <= "1011"; wait for 20 ns; B <= "0101"; wait for 20 ns; A <= "1001"; wait for 20 ns; B <= "0100"; wait for 20 ns; end process; end JMJS_Logic;