library ieee;
use ieee.std_logic_1164.all;

entity concept1_tb is

end concept1_tb;

architecture JMJS_Logic of concept1_tb is
    signal con : std_logic;
    signal data_in1, data_in2 : std_logic;
    signal data_out       : std_logic;

    component concept1
        port (con : in std_logic;
	      data_in1, data_in2 : in  std_logic;
              data_out : out std_logic);
    end component;

begin
    U0 : concept1 port map(con, data_in1, data_in2, data_out);

    process
    begin
	con <= '0'; wait for 20 ns;
	con <= '1'; wait for 60 ns;
	con <= '0'; wait for 60 ns;
	con <= '1'; wait for 20 ns;
    end process;

    process
    begin
	data_in1 <= '0'; wait for 40 ns;
	data_in1 <= '1'; wait for 40 ns;
	data_in1 <= '0'; wait for 60 ns;
	data_in1 <= '1'; wait for 20 ns;
    end process;

    process
    begin
	data_in2 <= '1'; wait for 60 ns;
	data_in2 <= '0'; wait for 60 ns;
	data_in2 <= '1'; wait for 40 ns;
    end process;

end JMJS_Logic;