library ieee; use ieee.std_logic_1164.all; entity concept2_1_tb is end concept2_1_tb; architecture JMJS_Logic of concept2_1_tb is signal con, data_in : std_logic; signal data_out : std_logic; component concept2_1 port (con, data_in : in std_logic; data_out : out std_logic); end component; begin U0 : concept2_1 port map(con, data_in, data_out); process begin con <= '0'; wait for 40 ns; con <= '1'; wait for 80 ns; con <= '0'; wait for 40 ns; con <= '1'; wait for 40 ns; con <= '0'; wait for 40 ns; end process; process begin data_in <= '0'; wait for 20 ns; data_in <= '1'; wait for 60 ns; data_in <= '0'; wait for 40 ns; data_in <= '1'; wait for 100 ns; data_in <= '0'; wait for 20 ns; end process; end JMJS_Logic;