library ieee;
use ieee.std_logic_1164.all;

entity concept4_tb is

end concept4_tb;

architecture JMJS_Logic of concept4_tb is
    signal con : std_logic;
    signal clk : std_logic;
    signal data_in1, data_in2 : std_logic;
    signal data_out : std_logic;

    component concept4
        port(con : in std_logic;
             clk : in std_logic;
             data_in1, data_in2 : in  std_logic;
             data_out : out std_logic);
    end component;

begin
    U0 : concept4 port map(con, clk, data_in1, data_in2, data_out);
    
    process
    begin
        wait for 2 ns;
	con <= '0'; wait for 20 ns;
	con <= '1'; wait for 60 ns;
	con <= '0'; wait for 80 ns;
	con <= '1'; wait for 80 ns;
	con <= '0'; wait for 60 ns;
    end process;

    process
    begin
        wait for 2 ns;
	data_in1 <= '0'; wait for 60 ns;
	data_in1 <= '1'; wait for 60 ns;
	data_in1 <= '0'; wait for 80 ns;
	data_in1 <= '1'; wait for 60 ns;
    end process;

    process
    begin
        wait for 2 ns;
	data_in2 <= '0'; wait for 40 ns;
	data_in2 <= '1'; wait for 60 ns;
	data_in2 <= '0'; wait for 80 ns;
	data_in2 <= '1'; wait for 60 ns;
	data_in2 <= '0'; wait for 20 ns;
    end process;
     
    process
    begin
        clk <= '0'; wait for 20 ns;
	clk <= '1'; wait for 20 ns;
    end process;

end JMJS_Logic;