library ieee;
use ieee.std_logic_1164.all;

entity decoder38_tb is

end decoder38_tb;

architecture JMJS_Logic of decoder38_tb is
    signal data_in  : std_logic_vector(2 downto 0);
    signal data_out : std_logic_vector(7 downto 0);
   
    component decoder38
        port ( data_in  : in std_logic_vector(2 downto 0);	   
	       data_out : out std_logic_vector(7 downto 0));
    end component;

begin
    U0 : decoder38 port map( data_in, data_out);

    process
    begin
        data_in <= "000"; wait for 50 ns;
        data_in <= "010"; wait for 50 ns;
        data_in <= "110"; wait for 50 ns;
	data_in <= "001"; wait for 50 ns;
	data_in <= "101"; wait for 50 ns;
	data_in <= "011"; wait for 50 ns;
	data_in <= "100"; wait for 50 ns;
    end process;
end JMJS_Logic;