library ieee; use ieee.std_logic_1164.all; entity encoder83_tb is end encoder83_tb; architecture JMJS_Logic of encoder83_tb is signal data_in : std_logic_vector(7 downto 0); signal data_out : std_logic_vector(2 downto 0); component encoder83 port ( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(2 downto 0)); end component; begin U0 : encoder83 port map( data_in, data_out ); process begin data_in <= "00001111"; wait for 50 ns; data_in <= "00000001"; wait for 50 ns; data_in <= "00100000"; wait for 50 ns; data_in <= "00000100"; wait for 50 ns; data_in <= "10000000"; wait for 50 ns; data_in <= "00100100"; wait for 50 ns; data_in <= "01000000"; end process; end JMJS_Logic;