library ieee; use ieee.std_logic_1164.all; entity falling_edge_detector_tb is end falling_edge_detector_tb; architecture JMJS_Logic of falling_edge_detector_tb is signal clk, data : std_logic; signal y_out : std_logic; component falling_edge_detector port(clk, data : in std_logic; y_out : out std_logic); end component; begin U0 : falling_edge_detector port map(clk, data, y_out); process begin clk <= '0'; wait for 10 ns; clk <= '1'; wait for 10 ns; end process; process begin wait for 1 ns; data <= '0'; wait for 10 ns; data <= '1'; wait for 100 ns; data <= '0'; wait for 100 ns; end process; end JMJS_Logic;