library ieee; use ieee.std_logic_1164.all; entity key is port (clk, rst : in std_logic; keypad : in std_logic_vector(7 downto 0); door, beep : out std_logic); end key; architecture JMJS_Logic of key is type states is (state0, state1, state2, state3, state4, Err1, Err2, Err3, Err4); signal state : states; signal key_en1, key_en : std_logic; begin process(clk, rst, keypad) begin key_en <= keypad(0) or keypad(1) or keypad(2) or keypad(3) or keypad(4) or keypad(5) or keypad(6) or keypad(7); if (clk'event and clk='1') then key_en1 <= key_en; end if; if (rst = '1') then state <= state0; elsif (clk'event and clk='1') then case state is when state0 => if (key_en1='0' and key_en='1') then if (keypad(3)='1') then state <= state1; else state <= Err1; end if; end if; when state1 => if (key_en1='0' and key_en='1') then if (keypad(7)='1') then state <= state2; else state <= Err2; end if; end if; when state2 => if (key_en1='0' and key_en='1') then if (keypad(2)='1') then state <= state3; else state <= Err3; end if; end if; when state3 => if (key_en1='0' and key_en='1') then if (keypad(5)='1') then state <= state4; else state <= Err4; end if; end if; when state4 => state <= state0; when Err1 => if (key_en1='0' and key_en = '1') then state <= Err2; else state <= Err1; end if; when Err2 => if (key_en1='0' and key_en = '1') then state <= Err3; else state <= Err2; end if; when Err3 => if (key_en1='0' and key_en = '1') then state <= Err4; else state <= Err3; end if; when Err4 => state <= state0; end case; end if; end process; process (clk) begin if (rst = '1') then door <= '0'; beep <= '0'; elsif (clk'event and clk='1') then case state is when state4 => door <= '1'; beep <= '0'; when Err4 => door <= '0'; beep <= '1'; when others => door <= '0'; beep <= '0'; end case; end if; end process; end JMJS_Logic;