library ieee;
use ieee.std_logic_1164.all;

entity key_tb is

end key_tb;

architecture JMJS_Logic of key_tb is
    signal clk, rst   : std_logic;
    signal keypad     : std_logic_vector(7 downto 0);
    signal door, beep : std_logic;

    component key
        port (clk, rst   : in std_logic;
	      keypad     : in std_logic_vector(7 downto 0);
	      door, beep : out std_logic);
    end component;

begin
    U0 : key port map(clk, rst, keypad, door, beep);

    process
    begin
        clk <= '0'; wait for 5 ns;
	clk <= '1'; wait for 5 ns;
    end process;

    process
    begin
        rst <= '1'; wait for 10 ns;
	rst <= '0'; wait;
    end process;

    process
    begin
        wait for 2 ns;
	--right value
	keypad <= "00000000"; wait for 20 ns;
        keypad <= "00001000"; wait for 20 ns;
	keypad <= "00000000"; wait for 10 ns;
	keypad <= "10000000"; wait for 20 ns;
	keypad <= "00000000"; wait for 10 ns;
	keypad <= "00000100"; wait for 20 ns;
	keypad <= "00000000"; wait for 10 ns;
	keypad <= "00100000"; wait for 20 ns;
	keypad <= "00000000"; wait for 10 ns;
	--wrong value
	keypad <= "00001000"; wait for 20 ns;
	keypad <= "00000000"; wait for 10 ns;
	keypad <= "01000000"; wait for 20 ns;
	keypad <= "00000000"; wait for 10 ns;
	keypad <= "00100000"; wait for 20 ns;
	keypad <= "00000000"; wait for 10 ns;
	keypad <= "00001000"; wait for 20 ns;
	keypad <= "00000000"; wait for 10 ns;
    end process;

end JMJS_Logic;