library ieee;
use ieee.std_logic_1164.all;

entity mealy_machine is
   port(clk, rst, x : in std_logic;
        y           : out std_logic_vector(2 downto 0));
end mealy_machine;

architecture JMJS_logic of mealy_machine is
    type states is (s0, s1, s2, s3);
    signal state : states;
begin
    p1 : process(clk, rst)
    begin
        if(rst = '1') then
	    state <= s0;
	elsif(clk'event and clk = '1') then
	    case state is
	        when s0 =>
		    if x = '1' then
		        state <= s1;
		    end if;
		when s1 =>
		    if x = '0' then
		        state <= s2;
		    end if;
		when s2 =>
		    if x = '1' then
		        state <= s3;
		    end if;
		when s3 =>
		    if x = '0' then
		       state <= s0;
		    end if;
            end case;
	end if;
    end process;

    p2 : process(state, x)
    begin
        case state is
	    when s0 => 
	        if x = '1' then
		    y <= "000";
		else
		    y <= "111";
		end if;
	    when s1 => 
	        if x = '1' then
		    y <= "000";
		else
		    y <= "001";
		end if;
	    when s2 => 
	        if x = '1' then
		    y <= "011";
		else
		    y <= "001";
		end if;
	    when s3 => 
	        if x = '1' then
		    y <= "011";
		else
		    y <= "111";
		end if;
	end case;
    end process;

end JMJS_Logic;