--------------------------------------------------------------------------------------------------- -- -- Title : Test Bench for mini_vending_machine -- Design : mini_vending_machine -- Author : Jamie Byun -- Company : JMJS -- --------------------------------------------------------------------------------------------------- -- -- File : $DSN\src\TestBench\mini_vending_machine_tb.vhd -- Generated : 2002-12-03, ¿ÀÈÄ 3:11 -- From : $DSN\src\mini_vending_machine.vhd -- By : Active-HDL Built-in Test Bench Generator ver. 1.2s -- --------------------------------------------------------------------------------------------------- -- -- Description : Automatically generated Test Bench for mini_vending_machine_tb -- --------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity mini_vending_machine_tb is end mini_vending_machine_tb; architecture JMJS_Logic of mini_vending_machine_tb is -- Component declaration of the tested unit component mini_vending_machine port( rst : in std_logic; clk : in std_logic; coffee_button : in std_logic; orange_button : in std_logic; tea_button : in std_logic; change_return : in std_logic; coin_500 : in std_logic; coin_100 : in std_logic; coin_50 : in std_logic; coin_10 : in std_logic; change : out std_logic_vector(7 downto 0); coffee_out : out std_logic; tea_out : out std_logic; orange_out : out std_logic ); end component; -- Stimulus signals - signals mapped to the input and inout ports of tested entity signal rst : std_logic; signal clk : std_logic; signal coffee_button : std_logic; signal orange_button : std_logic; signal tea_button : std_logic; signal change_return : std_logic; signal coin_500 : std_logic; signal coin_100 : std_logic; signal coin_50 : std_logic; signal coin_10 : std_logic; -- Observed signals - signals mapped to the output ports of tested entity signal change : std_logic_vector(7 downto 0); signal coffee_out : std_logic; signal tea_out : std_logic; signal orange_out : std_logic; begin -- Unit Under Test port map UUT : mini_vending_machine port map ( rst => rst, clk => clk, coffee_button => coffee_button, orange_button => orange_button, tea_button => tea_button, change_return => change_return, coin_500 => coin_500, coin_100 => coin_100, coin_50 => coin_50, coin_10 => coin_10, change => change, coffee_out => coffee_out, tea_out => tea_out, orange_out => orange_out ); process begin clk <= '0'; wait for 10 ns; clk <= '1'; wait for 10 ns; end process; process begin rst <= '1'; wait for 10 ns; rst <= '0'; wait; end process; process begin coin_500 <= '0'; coin_100 <= '0'; coin_50 <= '0'; coin_10 <= '0'; coffee_button <= '0'; tea_button <= '0'; orange_button <='0'; change_return <= '0'; wait for 20 ns; coin_100 <= '1'; wait for 60 ns; coin_100 <= '0'; coffee_button <= '1'; wait for 20 ns; coffee_button <= '0'; wait for 20 ns; coin_100 <= '1'; wait for 20 ns; coin_100 <= '0'; coin_50 <= '1'; wait for 20 ns; coin_50 <= '0'; tea_button <= '1'; wait for 20 ns; tea_button <= '0'; wait for 20 ns; coin_500 <= '1'; wait for 20 ns; coin_500 <= '0'; orange_button <= '1'; wait for 20 ns; orange_button <= '0'; wait for 20 ns; change_return <= '1'; wait for 20 ns; change_return <= '0'; wait; end process; end JMJS_Logic;