library ieee;
use ieee.std_logic_1164.all;

entity moore_machine_tb is

end moore_machine_tb;

architecture JMJS_Logic of moore_machine_tb is
    signal clk, rst, x : std_logic;
    signal y           : std_logic_vector(2 downto 0);

    component moore_machine
        port(clk, rst, x : in std_logic;
	     y           : out std_logic_vector(2 downto 0));
    end component;

begin
    U0 : moore_machine port map(clk, rst, x, y);

    process
    begin
        clk <= '0'; wait for 5 ns;
	clk <= '1'; wait for 5 ns;
    end process;

    process
    begin
        rst <= '0'; wait for 10 ns;
	rst <= '1'; wait for 10 ns;
	rst <= '0'; wait;
    end process;

    process
    begin
        wait for 2 ns;
        x <= '0'; wait for 30 ns;
	x <= '1'; wait for 15 ns;
	x <= '0'; wait for 20 ns;
	x <= '1'; wait for 30 ns;
	x <= '0'; wait for 20 ns;
    end process;

end JMJS_Logic;