library ieee;
use ieee.std_logic_1164.all;

entity rising_edge_detector is
   port(clk, data : in std_logic;
        y_out : out std_logic);
end rising_edge_detector;

architecture JMJS_Logic of rising_edge_detector is
    signal data1 : std_logic;
begin
    process(clk, data, data1)
    begin
        if(clk'event and clk = '1') then
            data1 <= data;
	    if(data1 = '0' and data = '1') then
	        y_out <= '1';
            else
	        y_out <= '0';
	    end if;
        end if;
    end process;
end JMJS_Logic;