library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity stop_watch is
	port (rst, go_stop : in std_logic;
	      clk          : in std_logic;
	      out_time     : out std_logic_vector(5 downto 0 ));
end stop_watch;

architecture JMJS_Logic of stop_watch is
	type states is (stop, go);
	signal state : states;
	signal sec : std_logic_vector(5 downto 0);
begin
	process(rst, clk)
	begin
		if(rst = '1') then
			state <= stop;	
		elsif(clk'event and clk='1') then
			case state is
				when stop =>
					if(go_stop = '1') then
						state <= go;
					else
						state <= stop;
					end if;
				when go =>
					if(go_stop = '1') then
						state <= stop;
					else
						state <= go;
					end if;
			end case;
		end if;
	end process;

	process(clk)
	begin
		if (rst = '1') then
			sec <= "000000";
		elsif (clk'event and clk='1') then
			if (state = go) then
				if (sec = "111011") then
					sec <= "000000";
				else
					sec <= sec + 1;
				end if;
			end if;
		end if;
	end process;
	out_time <= sec;

end JMJS_Logic;