library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity stop_watch_tb is

end stop_watch_tb;

architecture JMJS_Logic of stop_watch_tb is
    signal clk, rst : std_logic;
    signal go_stop : std_logic;
    signal out_time    : std_logic_vector(5 downto 0);

    component stop_watch
        port(rst, go_stop : in std_logic;
	     clk          : in std_logic;
             out_time     : out std_logic_vector(5 downto 0));
    end component;    
begin
    
    U0 : stop_watch port map(rst, go_stop, clk, out_time);

    process
    begin
        clk <= '0';	wait for 10 ns;
	clk <= '1';	wait for 10 ns;
    end process;

    process
    begin
        rst <= '0'; wait for 5 ns;
        rst <= '1'; wait for 20 ns;
	rst <= '0'; wait;
    end process;

    process
    begin
    	wait for 1 ns;
    	go_stop <= '0'; wait for 40 ns;
	go_stop <= '1'; wait for 20 ns;
	go_stop <= '0'; wait for 200 ns;
	go_stop <= '1'; wait for 20 ns;
    end process;

end JMJS_Logic;