library ieee;
use ieee.std_logic_1164.all;

entity tri_state_tb is

end tri_state_tb;

architecture JMJS_Logic of tri_state_tb is
    signal en : std_logic;
    signal data_in : std_logic_vector(3 downto 0);
    signal data_out : std_logic_vector(3 downto 0);

    component tri_state
        port(en : in std_logic;
             data_in  : in std_logic_vector(3 downto 0);
             data_out : out std_logic_vector(3 downto 0));
    end component;
begin

    U0 : tri_state port map(en, data_in, data_out);

    process
    begin
        en <= '0'; wait for 20 ns;
	en <= '1'; wait for 50 ns;
	en <= '0'; wait for 30 ns;
	en <= '1'; wait for 50 ns;
    end process;

    process
    begin
        wait for 1 ns;
	data_in <= "1100"; wait for 50 ns;
	data_in <= "0101"; wait for 50 ns;
	data_in <= "0011"; wait for 50 ns;
    end process;

end JMJS_Logic;