library ieee;
use ieee.std_logic_1164.all;

entity two_input is
    port(A, B : in std_logic;
         AandB, AorB, notA, notB : out std_logic);
end two_input;

architecture JMJS_Logic of two_input is
begin
    AandB <= A and B;
    AorB  <= A or B;
    notA  <= not A;
    notB <= not B;

end JMJS_Logic;