library ieee;
use ieee.std_logic_1164.all;

entity two_input_tb is

end two_input_tb;

architecture JMJS_Logic of two_input_tb is
    signal A, B : std_logic;
    signal AandB, AorB, notA, notB : std_logic;

    component two_input
        port(A, B : in std_logic;
	     AandB, AorB, notA, notB : out std_logic);
    end component;
begin

    U0 : two_input port map(A, B, AandB, AorB, notA, notB);

    process
    begin
        A <= '0';
	wait for 20 ns;
	A <= '1';
	wait for 40 ns;
	A <= '0';
	wait for 60 ns;
	A <= '1';
	wait for 60 ns;
    end process;

    process
    begin
        B <= '0';
	wait for 40 ns;
	B <= '1';
	wait for 60 ns;
	B <= '0';
	wait for 40 ns;
	B <= '1';
	wait for 20 ns;
	B <= '0';
	wait for 20 ns;
    end process;

end JMJS_Logic;