library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity up_count is
    port(clk, rst : in  std_logic;
         c_out    : buffer std_logic_vector(11 downto 0));
end up_count;

architecture JMJS_Logic of up_count is
begin
    process(clk, rst)
    begin
        if(rst = '1') then
	    c_out <= (others => '0');
	elsif(clk'event and clk= '1') then
	    c_out <= c_out + '1';
	end if;
    end process;
end JMJS_Logic;