library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity up_count_tb is

end up_count_tb;

architecture JMJS_Logic of up_count_tb is
    signal clk, rst : std_logic;
    signal c_out    : std_logic_vector(11 downto 0);

    component up_count
        port(clk, rst : in  std_logic;
             c_out    : buffer std_logic_vector(11 downto 0));
    end component;    
begin
    
    U0 : up_count port map(clk, rst, c_out);

    process
    begin
        clk <= '0';	wait for 10 ns;
	clk <= '1';	wait for 10 ns;
    end process;

    process
    begin
        rst <= '0'; wait for 20 ns;
        rst <= '1'; wait for 20 ns;
	rst <= '0'; wait for 300 ns;
	rst <= '1'; wait for 40 ns;
	rst <= '0'; wait for 500 ns;
    end process;

end JMJS_Logic;