library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity updown_count is port(clk, updn, rst : in std_logic; c_out : buffer std_logic_vector(11 downto 0)); end updown_count; architecture JMJS_Logic of updown_count is begin process(clk, rst) begin if(rst = '1') then c_out <= (others => '0'); elsif(clk'event and clk = '1') then if(updn = '1') then c_out <= c_out + 1; else c_out <= c_out - 1; end if; end if; end process; end JMJS_Logic;