library ieee;
use ieee.std_logic_1164.all;

entity updown_count_tb is

end updown_count_tb;

architecture JMJS_Logic of updown_count_tb is
    signal clk, updn, rst : std_logic;
    signal c_out : std_logic_vector(11 downto 0);

    component updown_count
        port(clk, updn, rst : in std_logic;
	     c_out : buffer std_logic_vector(11 downto 0));
    end component;

begin
    U0 : updown_count port map(clk, updn, rst, c_out);

    process
    begin
        clk <= '0'; wait for 10 ns;
	clk <= '1'; wait for 10 ns;
    end process;

    process
    begin
        rst <= '0'; wait for 5 ns;
	rst <= '1'; wait for 10 ns;
	rst <= '0'; wait;
    end process;

    process
    begin
        wait for 1 ns;
        updn <= '1'; wait for 200 ns;
	updn <= '0'; wait for 180 ns;
	updn <= '1'; wait for 150 ns;
    end process;

end JMJS_Logic;