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사과장수  Study-HDL  Script Tip  Perl Tip  C Memo  Python  게시물: 93 건, 현재: 1 / 1 쪽 [1] 번호 제       목 작성자 등록일 방문 95  draw_hexa.v JMJS 10.6.17 2241 94  jmjsxram3.v JMJS 10.4.9 1958 93  Verilog document JMJS 11.1.24 2539 92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2115 91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3618 90  gtkwave PC version JMJS 09.3.30 1890 89  ncsim option example JMJS 08.12.1 4290 88  [영상]keywords for web search JMJS 08.12.1 1914 87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6298 86  ncverilog option example JMJS 10.6.8 7700 85  [Verilog]Latch example JMJS 08.12.1 2507 84  Pad verilog example JMJS 01.3.16 4479 83  [ModelSim] vector JMJS 01.3.16 2119 82  RTL Code 분석순서 JMJS 09.4.29 2417 81  [temp]PIPE JMJS 08.10.2 1788 80  [temp]always-forever 무한루프 JMJS 08.10.2 1848 79  YCbCr2RGB.v JMJS 10.5.12 2071 78  [VHDL]rom64x8 JMJS 09.3.27 1672 77  [function]vector_compare JMJS 02.6.19 1629 76  [function]vector2integer JMJS 02.6.19 1721 75  [VHDL]ram8x4x8 JMJS 08.12.1 1585 74  [예]shift JMJS 02.6.19 1952 73  test JMJS 09.7.20 1704 72  test JMJS 09.7.20 1526 71  test JMJS 09.7.20 1462 70  test JMJS 09.7.20 1552 69  test JMJS 09.7.20 1599 68  test JMJS 09.7.20 1510 67  test JMJS 09.7.20 1422 66  test JMJS 09.7.20 1398 65  test JMJS 09.7.20 1493 64  test JMJS 09.7.20 1777 63  test JMJS 09.7.20 1764 62  test JMJS 09.7.20 1684 61  VHDL의 연산자 우선순위 JMJS 09.7.20 3620 60  test JMJS 09.7.20 1425 59  test JMJS 09.7.20 1506 58  test JMJS 09.7.20 1541 57  test JMJS 09.7.20 1467 56  test JMJS 09.7.20 1508 55  verilog 학과 샘플강의 JMJS 16.5.30 2230 54  [verilog]create_generated_clock JMJS 15.4.28 2122 53  [Verilog]JDIFF JMJS 14.7.4 1390 52  [verilog]parameter definition JMJS 14.3.5 1644 51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4623 50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2373 49  Verdi JMJS 10.4.22 3084 48  draw hexa JMJS 10.4.9 1732 47  asfifo - Async FIFO JMJS 10.4.8 1546 46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3233 45  synplify batch JMJS 10.3.8 2312 44  전자시계 Type A JMJS 08.11.28 1803 43  I2C Webpage JMJS 08.2.25 1674 42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6139 41  [Verilog]vstring JMJS 17.9.27 1925 40  Riviera Simple Case JMJS 09.4.29 3102 39  [VHDL]DES Example JMJS 07.6.15 2799 38  [verilog]RAM example JMJS 09.6.5 2596 37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1813 36  Jamie's VHDL Handbook JMJS 08.11.28 2466 35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3103 34  RTL Job JMJS 09.4.29 1964 33  [VHDL]type example - package TYPES JMJS 06.2.2 1652 32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9662 30  [verilog]array_module JMJS 05.12.8 2033 29  [verilog-2001]generate JMJS 05.12.8 3272 28  protected JMJS 05.11.18 1868 27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2700 26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1742 25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2286 23  Array Of Array JMJS 04.8.16 1866 22  dumpfile, dumpvars JMJS 04.7.19 3486 21  Vending Machine Jamie 02.12.16 10097 20  Mini Vending Machine1 Jamie 02.12.10 6808 19  Mini Vending Machine Jamie 02.12.6 9744 18  Key Jamie 02.11.29 4866 17  Stop Watch Jamie 02.11.25 5605 16  Mealy Machine Jamie 02.8.29 6641 15  Moore Machine Jamie 02.8.29 17352 14  Up Down Counter Jamie 02.8.29 3869 13  Up Counter Jamie 02.8.29 2585 12  Edge Detecter Jamie 02.8.29 2843 11  Concept4 Jamie 02.8.28 1943 10  Concept3 Jamie 02.8.28 1893 9  Concept2_1 Jamie 02.8.28 1786 8  Concept2 Jamie 02.8.28 1845 7  Concept1 Jamie 02.8.26 2086 6  Tri State Buffer Jamie 02.8.26 3376 5  8x3 Encoder Jamie 02.8.28 4031 4  3x8 Decoder Jamie 02.8.28 3716 3  4bit Comparator Jamie 02.8.26 3085 2  가위 바위 보 게임 Jamie 02.8.26 5492 1  Two Input Logic Jamie 02.8.26 2306 [1]