설계이야기

사과장수  Study-HDL  Script Tip  Perl Tip  C Memo  Python  게시물: 93 건, 현재: 1 / 1 쪽 [1] 번호 제       목 작성자 등록일 방문 95  draw_hexa.v JMJS 10.6.17 2356 94  jmjsxram3.v JMJS 10.4.9 2065 93  Verilog document JMJS 11.1.24 2650 92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2234 91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3737 90  gtkwave PC version JMJS 09.3.30 1990 89  ncsim option example JMJS 08.12.1 4409 88  [영상]keywords for web search JMJS 08.12.1 2028 87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6411 86  ncverilog option example JMJS 10.6.8 7817 85  [Verilog]Latch example JMJS 08.12.1 2607 84  Pad verilog example JMJS 01.3.16 4599 83  [ModelSim] vector JMJS 01.3.16 2226 82  RTL Code 분석순서 JMJS 09.4.29 2508 81  [temp]PIPE JMJS 08.10.2 1865 80  [temp]always-forever 무한루프 JMJS 08.10.2 1954 79  YCbCr2RGB.v JMJS 10.5.12 2152 78  [VHDL]rom64x8 JMJS 09.3.27 1750 77  [function]vector_compare JMJS 02.6.19 1707 76  [function]vector2integer JMJS 02.6.19 1804 75  [VHDL]ram8x4x8 JMJS 08.12.1 1660 74  [예]shift JMJS 02.6.19 2030 73  test JMJS 09.7.20 1783 72  test JMJS 09.7.20 1602 71  test JMJS 09.7.20 1536 70  test JMJS 09.7.20 1629 69  test JMJS 09.7.20 1677 68  test JMJS 09.7.20 1587 67  test JMJS 09.7.20 1496 66  test JMJS 09.7.20 1470 65  test JMJS 09.7.20 1568 64  test JMJS 09.7.20 1854 63  test JMJS 09.7.20 1845 62  test JMJS 09.7.20 1755 61  VHDL의 연산자 우선순위 JMJS 09.7.20 3707 60  test JMJS 09.7.20 1524 59  test JMJS 09.7.20 1578 58  test JMJS 09.7.20 1614 57  test JMJS 09.7.20 1541 56  test JMJS 09.7.20 1585 55  verilog 학과 샘플강의 JMJS 16.5.30 2347 54  [verilog]create_generated_clock JMJS 15.4.28 2231 53  [Verilog]JDIFF JMJS 14.7.4 1467 52  [verilog]parameter definition JMJS 14.3.5 1736 51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4705 50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2526 49  Verdi JMJS 10.4.22 3176 48  draw hexa JMJS 10.4.9 1803 47  asfifo - Async FIFO JMJS 10.4.8 1625 46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3317 45  synplify batch JMJS 10.3.8 2386 44  전자시계 Type A JMJS 08.11.28 1870 43  I2C Webpage JMJS 08.2.25 1751 42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6251 41  [Verilog]vstring JMJS 17.9.27 2025 40  Riviera Simple Case JMJS 09.4.29 3185 39  [VHDL]DES Example JMJS 07.6.15 2872 38  [verilog]RAM example JMJS 09.6.5 2679 37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1896 36  Jamie's VHDL Handbook JMJS 08.11.28 2536 35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3185 34  RTL Job JMJS 09.4.29 2043 33  [VHDL]type example - package TYPES JMJS 06.2.2 1725 32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 22.6.13 9754 30  [verilog]array_module JMJS 05.12.8 2113 29  [verilog-2001]generate JMJS 05.12.8 3385 28  protected JMJS 05.11.18 1949 27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2779 26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1813 25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2356 23  Array Of Array JMJS 04.8.16 1945 22  dumpfile, dumpvars JMJS 04.7.19 3571 21  Vending Machine Jamie 02.12.16 10195 20  Mini Vending Machine1 Jamie 02.12.10 6878 19  Mini Vending Machine Jamie 02.12.6 9813 18  Key Jamie 02.11.29 4967 17  Stop Watch Jamie 02.11.25 5731 16  Mealy Machine Jamie 02.8.29 6714 15  Moore Machine Jamie 02.8.29 17430 14  Up Down Counter Jamie 02.8.29 3950 13  Up Counter Jamie 02.8.29 2655 12  Edge Detecter Jamie 02.8.29 2909 11  Concept4 Jamie 02.8.28 2030 10  Concept3 Jamie 02.8.28 1963 9  Concept2_1 Jamie 02.8.28 1849 8  Concept2 Jamie 02.8.28 1914 7  Concept1 Jamie 02.8.26 2158 6  Tri State Buffer Jamie 02.8.26 3456 5  8x3 Encoder Jamie 02.8.28 4140 4  3x8 Decoder Jamie 02.8.28 3842 3  4bit Comparator Jamie 02.8.26 3158 2  가위 바위 보 게임 Jamie 02.8.26 5588 1  Two Input Logic Jamie 02.8.26 2396 [1]