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사과장수  Study-HDL  Script Tip  Perl Tip  C Memo  Python  게시물: 93 건, 현재: 1 / 1 쪽 [1] 번호 제       목 작성자 등록일 방문 95  draw_hexa.v JMJS 10.6.17 2229 94  jmjsxram3.v JMJS 10.4.9 1946 93  Verilog document JMJS 11.1.24 2526 92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2102 91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3604 90  gtkwave PC version JMJS 09.3.30 1878 89  ncsim option example JMJS 08.12.1 4278 88  [영상]keywords for web search JMJS 08.12.1 1904 87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6284 86  ncverilog option example JMJS 10.6.8 7687 85  [Verilog]Latch example JMJS 08.12.1 2496 84  Pad verilog example JMJS 01.3.16 4467 83  [ModelSim] vector JMJS 01.3.16 2108 82  RTL Code 분석순서 JMJS 09.4.29 2405 81  [temp]PIPE JMJS 08.10.2 1778 80  [temp]always-forever 무한루프 JMJS 08.10.2 1835 79  YCbCr2RGB.v JMJS 10.5.12 2060 78  [VHDL]rom64x8 JMJS 09.3.27 1663 77  [function]vector_compare JMJS 02.6.19 1619 76  [function]vector2integer JMJS 02.6.19 1704 75  [VHDL]ram8x4x8 JMJS 08.12.1 1574 74  [예]shift JMJS 02.6.19 1941 73  test JMJS 09.7.20 1693 72  test JMJS 09.7.20 1516 71  test JMJS 09.7.20 1451 70  test JMJS 09.7.20 1542 69  test JMJS 09.7.20 1589 68  test JMJS 09.7.20 1499 67  test JMJS 09.7.20 1413 66  test JMJS 09.7.20 1389 65  test JMJS 09.7.20 1483 64  test JMJS 09.7.20 1767 63  test JMJS 09.7.20 1755 62  test JMJS 09.7.20 1674 61  VHDL의 연산자 우선순위 JMJS 09.7.20 3610 60  test JMJS 09.7.20 1413 59  test JMJS 09.7.20 1497 58  test JMJS 09.7.20 1532 57  test JMJS 09.7.20 1458 56  test JMJS 09.7.20 1498 55  verilog 학과 샘플강의 JMJS 16.5.30 2218 54  [verilog]create_generated_clock JMJS 15.4.28 2108 53  [Verilog]JDIFF JMJS 14.7.4 1378 52  [verilog]parameter definition JMJS 14.3.5 1633 51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4612 50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2360 49  Verdi JMJS 10.4.22 3072 48  draw hexa JMJS 10.4.9 1719 47  asfifo - Async FIFO JMJS 10.4.8 1535 46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3223 45  synplify batch JMJS 10.3.8 2301 44  전자시계 Type A JMJS 08.11.28 1793 43  I2C Webpage JMJS 08.2.25 1663 42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6125 41  [Verilog]vstring JMJS 17.9.27 1912 40  Riviera Simple Case JMJS 09.4.29 3090 39  [VHDL]DES Example JMJS 07.6.15 2786 38  [verilog]RAM example JMJS 09.6.5 2586 37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1803 36  Jamie's VHDL Handbook JMJS 08.11.28 2454 35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3092 34  RTL Job JMJS 09.4.29 1952 33  [VHDL]type example - package TYPES JMJS 06.2.2 1643 32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9644 30  [verilog]array_module JMJS 05.12.8 2023 29  [verilog-2001]generate JMJS 05.12.8 3261 28  protected JMJS 05.11.18 1852 27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2686 26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1733 25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2277 23  Array Of Array JMJS 04.8.16 1852 22  dumpfile, dumpvars JMJS 04.7.19 3475 21  Vending Machine Jamie 02.12.16 10085 20  Mini Vending Machine1 Jamie 02.12.10 6799 19  Mini Vending Machine Jamie 02.12.6 9732 18  Key Jamie 02.11.29 4854 17  Stop Watch Jamie 02.11.25 5583 16  Mealy Machine Jamie 02.8.29 6633 15  Moore Machine Jamie 02.8.29 17341 14  Up Down Counter Jamie 02.8.29 3859 13  Up Counter Jamie 02.8.29 2577 12  Edge Detecter Jamie 02.8.29 2834 11  Concept4 Jamie 02.8.28 1935 10  Concept3 Jamie 02.8.28 1884 9  Concept2_1 Jamie 02.8.28 1775 8  Concept2 Jamie 02.8.28 1837 7  Concept1 Jamie 02.8.26 2076 6  Tri State Buffer Jamie 02.8.26 3367 5  8x3 Encoder Jamie 02.8.28 4021 4  3x8 Decoder Jamie 02.8.28 3706 3  4bit Comparator Jamie 02.8.26 3076 2  가위 바위 보 게임 Jamie 02.8.26 5482 1  Two Input Logic Jamie 02.8.26 2297 [1]