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protected
# 28 JMJS    05.11.18 11:05

`celldefine

module ...
...
`protected
a;lksdjfa;lksjef
`endprotected
...
`disable_portfaults
`nosuppress_faults
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 181
97  test plusargs value plusargs JMJS 24.9.5 249
96  color text JMJS 24.7.13 252
95  draw_hexa.v JMJS 10.6.17 2455
94  jmjsxram3.v JMJS 10.4.9 2188
93  Verilog document JMJS 11.1.24 2797
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2382
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3799
90  gtkwave PC version JMJS 09.3.30 2137
89  ncsim option example JMJS 08.12.1 4519
88  [영상]keywords for web search JMJS 08.12.1 2152
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6457
86  ncverilog option example JMJS 10.6.8 7993
85  [Verilog]Latch example JMJS 08.12.1 2734
84  Pad verilog example JMJS 01.3.16 4663
83  [ModelSim] vector JMJS 01.3.16 2353
82  RTL Code 분석순서 JMJS 09.4.29 2635
81  [temp]PIPE JMJS 08.10.2 2000
80  [temp]always-forever 무한루프 JMJS 08.10.2 2080
79  YCbCr2RGB.v JMJS 10.5.12 2307
78  [VHDL]rom64x8 JMJS 09.3.27 1887
77  [function]vector_compare JMJS 02.6.19 1831
76  [function]vector2integer JMJS 02.6.19 1929
75  [VHDL]ram8x4x8 JMJS 08.12.1 1798
74  [예]shift JMJS 02.6.19 2166
73  test JMJS 09.7.20 1953
72  test JMJS 09.7.20 1726
71  test JMJS 09.7.20 1671
70  test JMJS 09.7.20 1767
69  test JMJS 09.7.20 1808
68  test JMJS 09.7.20 1754
67  test JMJS 09.7.20 1666
66  test JMJS 09.7.20 1642
65  test JMJS 09.7.20 1748
64  test JMJS 09.7.20 1959
63  test JMJS 09.7.20 1982
62  test JMJS 09.7.20 1888
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3691
60  test JMJS 09.7.20 1658
59  test JMJS 09.7.20 1767
58  test JMJS 09.7.20 1731
57  test JMJS 09.7.20 1696
56  test JMJS 09.7.20 1736
55  verilog 학과 샘플강의 JMJS 16.5.30 2329
54  [verilog]create_generated_clock JMJS 15.4.28 2318
53  [Verilog]JDIFF JMJS 14.7.4 1583
52  [verilog]parameter definition JMJS 14.3.5 1857
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4810
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2582
49  Verdi JMJS 10.4.22 3304
48  draw hexa JMJS 10.4.9 1936
47  asfifo - Async FIFO JMJS 10.4.8 1783
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3419
45  synplify batch JMJS 10.3.8 2528
44  전자시계 Type A JMJS 08.11.28 2046
43  I2C Webpage JMJS 08.2.25 1890
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6042
41  [Verilog]vstring JMJS 17.9.27 2127
40  Riviera Simple Case JMJS 09.4.29 3259
39  [VHDL]DES Example JMJS 07.6.15 3017
38  [verilog]RAM example JMJS 09.6.5 2784
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2067
36  Jamie's VHDL Handbook JMJS 08.11.28 2734
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3361
34  RTL Job JMJS 09.4.29 2202
33  [VHDL]type example - package TYPES JMJS 06.2.2 1864
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9405
30  [verilog]array_module JMJS 05.12.8 2341
29  [verilog-2001]generate JMJS 05.12.8 3424
28  protected JMJS 05.11.18 2102
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2915
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1925
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2533
23  Array Of Array JMJS 04.8.16 2045
22  dumpfile, dumpvars JMJS 04.7.19 3656
21  Vending Machine Jamie 02.12.16 10124
20  Mini Vending Machine1 Jamie 02.12.10 7007
19  Mini Vending Machine Jamie 02.12.6 9860
18  Key Jamie 02.11.29 5022
17  Stop Watch Jamie 02.11.25 5706
16  Mealy Machine Jamie 02.8.29 6780
15  Moore Machine Jamie 02.8.29 18016
14  Up Down Counter Jamie 02.8.29 4116
13  Up Counter Jamie 02.8.29 2814
12  Edge Detecter Jamie 02.8.29 3030
11  Concept4 Jamie 02.8.28 2137
10  Concept3 Jamie 02.8.28 2116
9  Concept2_1 Jamie 02.8.28 2000
8  Concept2 Jamie 02.8.28 2092
7  Concept1 Jamie 02.8.26 2291
6  Tri State Buffer Jamie 02.8.26 3594
5  8x3 Encoder Jamie 02.8.28 4215
4  3x8 Decoder Jamie 02.8.28 3876
3  4bit Comparator Jamie 02.8.26 3255
2  가위 바위 보 게임 Jamie 02.8.26 5581
1  Two Input Logic Jamie 02.8.26 2497
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