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protected
# 28 JMJS    05.11.18 11:05

`celldefine

module ...
...
`protected
a;lksdjfa;lksjef
`endprotected
...
`disable_portfaults
`nosuppress_faults
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 195
97  test plusargs value plusargs JMJS 24.9.5 261
96  color text JMJS 24.7.13 262
95  draw_hexa.v JMJS 10.6.17 2467
94  jmjsxram3.v JMJS 10.4.9 2207
93  Verilog document JMJS 11.1.24 2810
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2397
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3816
90  gtkwave PC version JMJS 09.3.30 2158
89  ncsim option example JMJS 08.12.1 4540
88  [영상]keywords for web search JMJS 08.12.1 2171
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6467
86  ncverilog option example JMJS 10.6.8 8011
85  [Verilog]Latch example JMJS 08.12.1 2749
84  Pad verilog example JMJS 01.3.16 4678
83  [ModelSim] vector JMJS 01.3.16 2375
82  RTL Code 분석순서 JMJS 09.4.29 2653
81  [temp]PIPE JMJS 08.10.2 2017
80  [temp]always-forever 무한루프 JMJS 08.10.2 2102
79  YCbCr2RGB.v JMJS 10.5.12 2327
78  [VHDL]rom64x8 JMJS 09.3.27 1904
77  [function]vector_compare JMJS 02.6.19 1841
76  [function]vector2integer JMJS 02.6.19 1942
75  [VHDL]ram8x4x8 JMJS 08.12.1 1809
74  [예]shift JMJS 02.6.19 2183
73  test JMJS 09.7.20 1973
72  test JMJS 09.7.20 1734
71  test JMJS 09.7.20 1691
70  test JMJS 09.7.20 1785
69  test JMJS 09.7.20 1828
68  test JMJS 09.7.20 1773
67  test JMJS 09.7.20 1686
66  test JMJS 09.7.20 1665
65  test JMJS 09.7.20 1766
64  test JMJS 09.7.20 1973
63  test JMJS 09.7.20 2001
62  test JMJS 09.7.20 1906
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3715
60  test JMJS 09.7.20 1668
59  test JMJS 09.7.20 1786
58  test JMJS 09.7.20 1748
57  test JMJS 09.7.20 1712
56  test JMJS 09.7.20 1759
55  verilog 학과 샘플강의 JMJS 16.5.30 2341
54  [verilog]create_generated_clock JMJS 15.4.28 2326
53  [Verilog]JDIFF JMJS 14.7.4 1590
52  [verilog]parameter definition JMJS 14.3.5 1869
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4818
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2590
49  Verdi JMJS 10.4.22 3328
48  draw hexa JMJS 10.4.9 1945
47  asfifo - Async FIFO JMJS 10.4.8 1793
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3440
45  synplify batch JMJS 10.3.8 2547
44  전자시계 Type A JMJS 08.11.28 2063
43  I2C Webpage JMJS 08.2.25 1908
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6060
41  [Verilog]vstring JMJS 17.9.27 2141
40  Riviera Simple Case JMJS 09.4.29 3269
39  [VHDL]DES Example JMJS 07.6.15 3034
38  [verilog]RAM example JMJS 09.6.5 2806
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2088
36  Jamie's VHDL Handbook JMJS 08.11.28 2747
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3376
34  RTL Job JMJS 09.4.29 2215
33  [VHDL]type example - package TYPES JMJS 06.2.2 1873
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9416
30  [verilog]array_module JMJS 05.12.8 2358
29  [verilog-2001]generate JMJS 05.12.8 3445
28  protected JMJS 05.11.18 2117
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2931
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1934
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2544
23  Array Of Array JMJS 04.8.16 2060
22  dumpfile, dumpvars JMJS 04.7.19 3675
21  Vending Machine Jamie 02.12.16 10135
20  Mini Vending Machine1 Jamie 02.12.10 7023
19  Mini Vending Machine Jamie 02.12.6 9879
18  Key Jamie 02.11.29 5038
17  Stop Watch Jamie 02.11.25 5715
16  Mealy Machine Jamie 02.8.29 6795
15  Moore Machine Jamie 02.8.29 18049
14  Up Down Counter Jamie 02.8.29 4132
13  Up Counter Jamie 02.8.29 2826
12  Edge Detecter Jamie 02.8.29 3043
11  Concept4 Jamie 02.8.28 2146
10  Concept3 Jamie 02.8.28 2132
9  Concept2_1 Jamie 02.8.28 2020
8  Concept2 Jamie 02.8.28 2112
7  Concept1 Jamie 02.8.26 2300
6  Tri State Buffer Jamie 02.8.26 3609
5  8x3 Encoder Jamie 02.8.28 4231
4  3x8 Decoder Jamie 02.8.28 3895
3  4bit Comparator Jamie 02.8.26 3276
2  가위 바위 보 게임 Jamie 02.8.26 5590
1  Two Input Logic Jamie 02.8.26 2514
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