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protected
# 28 JMJS    05.11.18 11:05

`celldefine

module ...
...
`protected
a;lksdjfa;lksjef
`endprotected
...
`disable_portfaults
`nosuppress_faults
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 189
97  test plusargs value plusargs JMJS 24.9.5 254
96  color text JMJS 24.7.13 256
95  draw_hexa.v JMJS 10.6.17 2461
94  jmjsxram3.v JMJS 10.4.9 2199
93  Verilog document JMJS 11.1.24 2803
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2392
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3808
90  gtkwave PC version JMJS 09.3.30 2150
89  ncsim option example JMJS 08.12.1 4530
88  [영상]keywords for web search JMJS 08.12.1 2161
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6461
86  ncverilog option example JMJS 10.6.8 8005
85  [Verilog]Latch example JMJS 08.12.1 2741
84  Pad verilog example JMJS 01.3.16 4671
83  [ModelSim] vector JMJS 01.3.16 2365
82  RTL Code 분석순서 JMJS 09.4.29 2645
81  [temp]PIPE JMJS 08.10.2 2008
80  [temp]always-forever 무한루프 JMJS 08.10.2 2092
79  YCbCr2RGB.v JMJS 10.5.12 2318
78  [VHDL]rom64x8 JMJS 09.3.27 1896
77  [function]vector_compare JMJS 02.6.19 1835
76  [function]vector2integer JMJS 02.6.19 1937
75  [VHDL]ram8x4x8 JMJS 08.12.1 1803
74  [예]shift JMJS 02.6.19 2173
73  test JMJS 09.7.20 1965
72  test JMJS 09.7.20 1728
71  test JMJS 09.7.20 1685
70  test JMJS 09.7.20 1778
69  test JMJS 09.7.20 1819
68  test JMJS 09.7.20 1766
67  test JMJS 09.7.20 1678
66  test JMJS 09.7.20 1656
65  test JMJS 09.7.20 1757
64  test JMJS 09.7.20 1966
63  test JMJS 09.7.20 1992
62  test JMJS 09.7.20 1897
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3703
60  test JMJS 09.7.20 1662
59  test JMJS 09.7.20 1779
58  test JMJS 09.7.20 1741
57  test JMJS 09.7.20 1706
56  test JMJS 09.7.20 1748
55  verilog 학과 샘플강의 JMJS 16.5.30 2335
54  [verilog]create_generated_clock JMJS 15.4.28 2322
53  [Verilog]JDIFF JMJS 14.7.4 1587
52  [verilog]parameter definition JMJS 14.3.5 1864
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4815
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2587
49  Verdi JMJS 10.4.22 3317
48  draw hexa JMJS 10.4.9 1942
47  asfifo - Async FIFO JMJS 10.4.8 1789
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3434
45  synplify batch JMJS 10.3.8 2539
44  전자시계 Type A JMJS 08.11.28 2055
43  I2C Webpage JMJS 08.2.25 1902
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6052
41  [Verilog]vstring JMJS 17.9.27 2135
40  Riviera Simple Case JMJS 09.4.29 3262
39  [VHDL]DES Example JMJS 07.6.15 3026
38  [verilog]RAM example JMJS 09.6.5 2798
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2081
36  Jamie's VHDL Handbook JMJS 08.11.28 2742
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3370
34  RTL Job JMJS 09.4.29 2206
33  [VHDL]type example - package TYPES JMJS 06.2.2 1871
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9412
30  [verilog]array_module JMJS 05.12.8 2354
29  [verilog-2001]generate JMJS 05.12.8 3438
28  protected JMJS 05.11.18 2111
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2923
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1930
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2541
23  Array Of Array JMJS 04.8.16 2055
22  dumpfile, dumpvars JMJS 04.7.19 3668
21  Vending Machine Jamie 02.12.16 10130
20  Mini Vending Machine1 Jamie 02.12.10 7017
19  Mini Vending Machine Jamie 02.12.6 9868
18  Key Jamie 02.11.29 5033
17  Stop Watch Jamie 02.11.25 5711
16  Mealy Machine Jamie 02.8.29 6790
15  Moore Machine Jamie 02.8.29 18042
14  Up Down Counter Jamie 02.8.29 4124
13  Up Counter Jamie 02.8.29 2822
12  Edge Detecter Jamie 02.8.29 3039
11  Concept4 Jamie 02.8.28 2142
10  Concept3 Jamie 02.8.28 2127
9  Concept2_1 Jamie 02.8.28 2015
8  Concept2 Jamie 02.8.28 2105
7  Concept1 Jamie 02.8.26 2295
6  Tri State Buffer Jamie 02.8.26 3605
5  8x3 Encoder Jamie 02.8.28 4225
4  3x8 Decoder Jamie 02.8.28 3891
3  4bit Comparator Jamie 02.8.26 3268
2  가위 바위 보 게임 Jamie 02.8.26 5586
1  Two Input Logic Jamie 02.8.26 2509
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