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protected

# 28

JMJS 05.11.18 11:05

`celldefine

module ...
...
`protected
a;lksdjfa;lksjef
`endprotected
...
`disable_portfaults
`nosuppress_faults

게시물: 96 건, 현재: 1 / 1 쪽
번호	제 목	작성자	등록일	방문
98	interface	JMJS	25.1.20	329
97	test plusargs value plusargs	JMJS	24.9.5	348
96	color text	JMJS	24.7.13	387
95	draw_hexa.v	JMJS	10.6.17	2543
94	jmjsxram3.v	JMJS	10.4.9	2442
93	Verilog document	JMJS	11.1.24	3038
92	[verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3;	JMJS	09.3.31	2625
91	[verilog]forever, repeat, strobe, realtime, ...	JMJS	09.7.6	4064
90	gtkwave PC version	JMJS	09.3.30	2429
89	ncsim option example	JMJS	08.12.1	4794
88	[영상]keywords for web search	JMJS	08.12.1	2391
87	[Verilog]fdisplay fopen fscanf	JMJS	11.1.24	6546
86	ncverilog option example	JMJS	10.6.8	8256
85	[Verilog]Latch example	JMJS	08.12.1	2993
84	Pad verilog example	JMJS	01.3.16	4929
83	[ModelSim] vector	JMJS	01.3.16	2621
82	RTL Code 분석순서	JMJS	09.4.29	2869
81	[temp]PIPE	JMJS	08.10.2	2265
80	[temp]always-forever 무한루프	JMJS	08.10.2	2339
79	YCbCr2RGB.v	JMJS	10.5.12	2535
78	[VHDL]rom64x8	JMJS	09.3.27	2083
77	[function]vector_compare	JMJS	02.6.19	1984
76	[function]vector2integer	JMJS	02.6.19	2188
75	[VHDL]ram8x4x8	JMJS	08.12.1	1924
74	[예]shift	JMJS	02.6.19	2379
73	test	JMJS	09.7.20	2223
72	test	JMJS	09.7.20	1791
71	test	JMJS	09.7.20	1938
70	test	JMJS	09.7.20	2028
69	test	JMJS	09.7.20	2077
68	test	JMJS	09.7.20	2013
67	test	JMJS	09.7.20	1948
66	test	JMJS	09.7.20	1894
65	test	JMJS	09.7.20	2015
64	test	JMJS	09.7.20	2209
63	test	JMJS	09.7.20	2244
62	test	JMJS	09.7.20	2136
61	VHDL의 연산자 우선순위	JMJS	09.7.20	3932
60	test	JMJS	09.7.20	1723
59	test	JMJS	09.7.20	2067
58	test	JMJS	09.7.20	1973
57	test	JMJS	09.7.20	1945
56	test	JMJS	09.7.20	1983
55	verilog 학과 샘플강의	JMJS	16.5.30	2430
54	[verilog]create_generated_clock	JMJS	15.4.28	2413
53	[Verilog]JDIFF	JMJS	14.7.4	1808
52	[verilog]parameter definition	JMJS	14.3.5	2089
51	[verilog]sformat fopen fscanf fwrite fclose	JMJS	12.1.31	5028
50	Verilog File I/0,Verilog file handling	JMJS	12.1.30	2687
49	Verdi	JMJS	10.4.22	3573
48	draw hexa	JMJS	10.4.9	2078
47	asfifo - Async FIFO	JMJS	10.4.8	1936
46	VHDL을 이용한 회로설계의 장점	JMJS	02.3.14	3615
45	synplify batch	JMJS	10.3.8	2810
44	전자시계 Type A	JMJS	08.11.28	2299
43	I2C Webpage	JMJS	08.2.25	2135
42	PC에서 간단히 Verilog 실행해보기 (Icarus Verilog)	JMJS	13.1.14	6242
41	[Verilog]vstring	JMJS	17.9.27	2341
40	Riviera Simple Case	JMJS	09.4.29	3433
39	[VHDL]DES Example	JMJS	07.6.15	3290
38	[verilog]RAM example	JMJS	09.6.5	3068
37	ROM example [VerilogHDL, RTL]	JMJS	04.5.27	2304
36	Jamie's VHDL Handbook	JMJS	08.11.28	2995
35	Dualport RAM example [VerilogHDL, RTL]	JMJS	04.5.27	3576
34	RTL Job	JMJS	09.4.29	2512
33	[VHDL]type example - package TYPES	JMJS	06.2.2	1972
32	[verilog]`define `ifdef `elsif `else `endif ...	JMJS	10.5.11	9641
30	[verilog]array_module	JMJS	05.12.8	2548
29	[verilog-2001]generate	JMJS	05.12.8	3691
28	protected	JMJS	05.11.18	2344
27	design에 latch가 있으면 안되나요?	JMJS	09.7.20	3087
26	bus의 데이타를 각 bit별로 출력하는 방법은?	JMJS	04.11.9	2077
25	component를 생성해서 다른 곳에서 호출하는 방법	JMJS	04.11.4	2708
23	Array Of Array	JMJS	04.8.16	2234
22	dumpfile, dumpvars	JMJS	04.7.19	3926
21	Vending Machine	Jamie	02.12.16	10366
20	Mini Vending Machine1	Jamie	02.12.10	7233
19	Mini Vending Machine	Jamie	02.12.6	10067
18	Key	Jamie	02.11.29	5268
17	Stop Watch	Jamie	02.11.25	5813
16	Mealy Machine	Jamie	02.8.29	6983
15	Moore Machine	Jamie	02.8.29	18334
14	Up Down Counter	Jamie	02.8.29	4355
13	Up Counter	Jamie	02.8.29	3044
12	Edge Detecter	Jamie	02.8.29	3264
11	Concept4	Jamie	02.8.28	2232
10	Concept3	Jamie	02.8.28	2328
9	Concept2_1	Jamie	02.8.28	2223
8	Concept2	Jamie	02.8.28	2309
7	Concept1	Jamie	02.8.26	2355
6	Tri State Buffer	Jamie	02.8.26	3905
5	8x3 Encoder	Jamie	02.8.28	4457
4	3x8 Decoder	Jamie	02.8.28	4098
3	4bit Comparator	Jamie	02.8.26	3476
2	가위 바위 보 게임	Jamie	02.8.26	5648
1	Two Input Logic	Jamie	02.8.26	2728

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