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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity ram8x4x8 is
port(
rst : in std_logic;
data : inout std_logic_vector (7 downto 0);
addr : in std_logic_vector (4 downto 0);
wr : in std_logic
);
end ram8x4x8;
architecture logic of ram8x4x8 is
type table8x4x8 is array (31 downto 0) of std_logic_vector (7 downto 0);
function v2i (bv: std_logic_vector (4 downto 0)) return integer is
variable result, abit : integer := 0;
variable count : integer := 0;
begin
bits : for I in bv'low to bv'high loop
abit := 0;
if bv(I) = '1' then
abit := 2**(I - bv'low);
end if;
result := result + abit;
count := count + 1;
exit bits when count = 5;
end loop bits;
return (result);
end v2i;
signal acell : table8x4x8;
signal iaddr : integer := 0;
begin
iaddr <= v2i(addr);
data_in: process (rst, wr, iaddr) begin
if(wr = '1') then
data <= "ZZZZZZZZ";
else
data <= acell (iaddr);
end if;
end process;
data_out: process (rst, wr, data, iaddr) begin
if(rst = '1') then
for I in 0 to 31 loop
acell (I) <= "00000000";
end loop;
if(wr = '1') then
acell (iaddr) <= data;
end if;
end process;
end logic;
----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity ram8x4x8_tb is
end ram8x4x8_tb;
architecture logic of ram8x4x8_tb is
component ram8x4x8
port(
rst : in std_logic;
data: inout std_logic_vector (7 downto 0);
addr: in std_logic_vector (4 downto 0);
wr: in std_logic
);
end component;
signal rst : std_logic;
signal data: std_logic_vector (7 downto 0);
signal addr: std_logic_vector (4 downto 0);
signal wr : std_logic;
begin
mem0 : ram8x4x8 port map (
rst => rst,
data => data,
addr => addr,
wr => wr
);
process begin
rst <= '0';
wait for 3 ns;
rst <= '1';
addr <= "00000";
data <= "01010101";
wr <= '0';
wait for 5 ns;
rst <= '0';
wait for 2 ns;
addr <= "00001";
data <= "01010101";
wr <= '1';
wait for 10 ns;
addr <= "00010";
data <= "01010101";
wr <= '1';
wait for 10 ns;
addr <= "00100";
data <= "01010101";
wr <= '1';
wait for 10 ns;
addr <= "01000";
data <= "01010101";
wr <= '1';
wait for 10 ns;
addr <= "01100";
data <= "ZZZZZZZZ";
wr <= '0';
wait for 10 ns;
addr <= "01000";
data <= "ZZZZZZZZ";
wr <= '0';
wait for 10 ns;
end process;
end logic;
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