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`define TC "1"
`define DD {"../../TV/TV",`TC,"/1_INPUT"}
module abc ();
initial begin
$display("%t INPUT_DB:%5s\n",$time,`DD);
end
endmodule
%cat test.v
`define ABC 1
`define ABC 2 //같은 Define 2번하면 Error나 Warning, 뒤에 Define문 값으로 치환됨? 혹은 앞의 값 유지?
...
`ifdef CARBON_MEM
reg [11:0] mem [0:15];
reg [3:0] addrb_q;
always @(posedge clka) if (~wea) mem[addra] <= dina;
always @(posedge clkb) if (~enb) addrb_q <= addrb;
`else
BLKMEMDP_V6_3 #(3,4) inst (.SINITA(dina),SINITB(addrb),.WEB());
`endif
...
%vsim +define+CARBON_MEM ... |
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