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Concept3
# 10 Jamie    02.8.28 16:39

1.Spec

À̹ø¿¡ ¼³¸íÇÒ conceptÀº data°¡ Ãâ·ÂµÉ ¶§ÀÇ clkÀÇ ¼øÀ§ÀÔ´Ï´Ù.
Block Diagram¿¡¼­ º¸µíÀÌ con signal¿¡ ¼±ÅÃµÈ ÀÔ·Â data°¡ clkÀÇ »ó½Â trigger¿¡¼­
Ãâ·ÂµË´Ï´Ù.
À̰ÍÀº ³ªÁß¿¡ °øºÎÇÒ flip flop°ú °ü·ÃµÈ ¾ÆÁÖ Áß¿äÇÑ °³³äÀÌÁö¿ä.
source¿Í block diagramÀ» ºñ±³Çϸ鼭 °øºÎÇϼ¼¿ä.

2.Input/Output



3.Timing



4.Block Diagram



5.RTL Code : concept3.vhd
  Test Vector : concept_tb.vhd

°Ô½Ã¹°: 96 °Ç, ÇöÀç: 1 / 1 ÂÊ
¹øÈ£ Á¦       ¸ñ ÀÛ¼ºÀÚ µî·ÏÀÏ ¹æ¹®
98  interface JMJS 25.1.20 346
97  test plusargs value plusargs JMJS 24.9.5 355
96  color text JMJS 24.7.13 410
95  draw_hexa.v JMJS 10.6.17 2555
94  jmjsxram3.v JMJS 10.4.9 2510
93  Verilog document JMJS 11.1.24 3088
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2693
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4132
90  gtkwave PC version JMJS 09.3.30 2524
89  ncsim option example JMJS 08.12.1 4872
88  [¿µ»ó]keywords for web search JMJS 08.12.1 2471
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6561
86  ncverilog option example JMJS 10.6.8 8332
85  [Verilog]Latch example JMJS 08.12.1 3059
84  Pad verilog example JMJS 01.3.16 5009
83  [ModelSim] vector JMJS 01.3.16 2691
82  RTL Code ºÐ¼®¼ø¼­ JMJS 09.4.29 2942
81  [temp]PIPE JMJS 08.10.2 2345
80  [temp]always-forever ¹«ÇÑ·çÇÁ JMJS 08.10.2 2428
79  YCbCr2RGB.v JMJS 10.5.12 2587
78  [VHDL]rom64x8 JMJS 09.3.27 2142
77  [function]vector_compare JMJS 02.6.19 2007
76  [function]vector2integer JMJS 02.6.19 2268
75  [VHDL]ram8x4x8 JMJS 08.12.1 1962
74  [¿¹]shift JMJS 02.6.19 2441
73  test JMJS 09.7.20 2300
72  test JMJS 09.7.20 1802
71  test JMJS 09.7.20 2032
70  test JMJS 09.7.20 2102
69  test JMJS 09.7.20 2152
68  test JMJS 09.7.20 2101
67  test JMJS 09.7.20 2038
66  test JMJS 09.7.20 1982
65  test JMJS 09.7.20 2098
64  test JMJS 09.7.20 2279
63  test JMJS 09.7.20 2331
62  test JMJS 09.7.20 2207
61  VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§ JMJS 09.7.20 3992
60  test JMJS 09.7.20 1732
59  test JMJS 09.7.20 2141
58  test JMJS 09.7.20 2054
57  test JMJS 09.7.20 2013
56  test JMJS 09.7.20 2060
55  verilog Çаú »ùÇð­ÀÇ JMJS 16.5.30 2442
54  [verilog]create_generated_clock JMJS 15.4.28 2437
53  [Verilog]JDIFF JMJS 14.7.4 1893
52  [verilog]parameter definition JMJS 14.3.5 2167
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5111
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2709
49  Verdi JMJS 10.4.22 3645
48  draw hexa JMJS 10.4.9 2101
47  asfifo - Async FIFO JMJS 10.4.8 1966
46  VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡ JMJS 02.3.14 3662
45  synplify batch JMJS 10.3.8 2867
44  ÀüÀڽðè Type A JMJS 08.11.28 2390
43  I2C Webpage JMJS 08.2.25 2205
42  PC¿¡¼­ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog) JMJS 13.1.14 6256
41  [Verilog]vstring JMJS 17.9.27 2384
40  Riviera Simple Case JMJS 09.4.29 3473
39  [VHDL]DES Example JMJS 07.6.15 3369
38  [verilog]RAM example JMJS 09.6.5 3142
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2378
36  Jamie's VHDL Handbook JMJS 08.11.28 3060
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3659
34  RTL Job JMJS 09.4.29 2587
33  [VHDL]type example - package TYPES JMJS 06.2.2 1992
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9703
30  [verilog]array_module JMJS 05.12.8 2604
29  [verilog-2001]generate JMJS 05.12.8 3755
28  protected JMJS 05.11.18 2430
27  design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä? JMJS 09.7.20 3136
26  busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº? JMJS 04.11.9 2101
25  component¸¦ »ý¼ºÇؼ­ ´Ù¸¥ °÷¿¡¼­ È£ÃâÇÏ´Â ¹æ¹ý JMJS 04.11.4 2746
23  Array Of Array JMJS 04.8.16 2289
22  dumpfile, dumpvars JMJS 04.7.19 3999
21  Vending Machine Jamie 02.12.16 10428
20  Mini Vending Machine1 Jamie 02.12.10 7295
19  Mini Vending Machine Jamie 02.12.6 10115
18  Key Jamie 02.11.29 5330
17  Stop Watch Jamie 02.11.25 5835
16  Mealy Machine Jamie 02.8.29 7053
15  Moore Machine Jamie 02.8.29 18389
14  Up Down Counter Jamie 02.8.29 4439
13  Up Counter Jamie 02.8.29 3136
12  Edge Detecter Jamie 02.8.29 3331
11  Concept4 Jamie 02.8.28 2246
10  Concept3 Jamie 02.8.28 2394
9  Concept2_1 Jamie 02.8.28 2276
8  Concept2 Jamie 02.8.28 2362
7  Concept1 Jamie 02.8.26 2364
6  Tri State Buffer Jamie 02.8.26 3980
5  8x3 Encoder Jamie 02.8.28 4532
4  3x8 Decoder Jamie 02.8.28 4158
3  4bit Comparator Jamie 02.8.26 3551
2  °¡À§ ¹ÙÀ§ º¸ °ÔÀÓ Jamie 02.8.26 5657
1  Two Input Logic Jamie 02.8.26 2801
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