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Concept3
# 10 Jamie    02.8.28 16:39

1.Spec

À̹ø¿¡ ¼³¸íÇÒ conceptÀº data°¡ Ãâ·ÂµÉ ¶§ÀÇ clkÀÇ ¼øÀ§ÀÔ´Ï´Ù.
Block Diagram¿¡¼­ º¸µíÀÌ con signal¿¡ ¼±ÅÃµÈ ÀÔ·Â data°¡ clkÀÇ »ó½Â trigger¿¡¼­
Ãâ·ÂµË´Ï´Ù.
À̰ÍÀº ³ªÁß¿¡ °øºÎÇÒ flip flop°ú °ü·ÃµÈ ¾ÆÁÖ Áß¿äÇÑ °³³äÀÌÁö¿ä.
source¿Í block diagramÀ» ºñ±³Çϸ鼭 °øºÎÇϼ¼¿ä.

2.Input/Output



3.Timing



4.Block Diagram



5.RTL Code : concept3.vhd
  Test Vector : concept_tb.vhd

°Ô½Ã¹°: 96 °Ç, ÇöÀç: 1 / 1 ÂÊ
¹øÈ£ Á¦       ¸ñ ÀÛ¼ºÀÚ µî·ÏÀÏ ¹æ¹®
98  interface JMJS 25.1.20 319
97  test plusargs value plusargs JMJS 24.9.5 342
96  color text JMJS 24.7.13 373
95  draw_hexa.v JMJS 10.6.17 2536
94  jmjsxram3.v JMJS 10.4.9 2408
93  Verilog document JMJS 11.1.24 3006
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2597
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4031
90  gtkwave PC version JMJS 09.3.30 2392
89  ncsim option example JMJS 08.12.1 4767
88  [¿µ»ó]keywords for web search JMJS 08.12.1 2368
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6540
86  ncverilog option example JMJS 10.6.8 8227
85  [Verilog]Latch example JMJS 08.12.1 2971
84  Pad verilog example JMJS 01.3.16 4897
83  [ModelSim] vector JMJS 01.3.16 2586
82  RTL Code ºÐ¼®¼ø¼­ JMJS 09.4.29 2845
81  [temp]PIPE JMJS 08.10.2 2240
80  [temp]always-forever ¹«ÇÑ·çÇÁ JMJS 08.10.2 2313
79  YCbCr2RGB.v JMJS 10.5.12 2509
78  [VHDL]rom64x8 JMJS 09.3.27 2063
77  [function]vector_compare JMJS 02.6.19 1967
76  [function]vector2integer JMJS 02.6.19 2163
75  [VHDL]ram8x4x8 JMJS 08.12.1 1910
74  [¿¹]shift JMJS 02.6.19 2357
73  test JMJS 09.7.20 2193
72  test JMJS 09.7.20 1785
71  test JMJS 09.7.20 1911
70  test JMJS 09.7.20 2008
69  test JMJS 09.7.20 2053
68  test JMJS 09.7.20 1982
67  test JMJS 09.7.20 1916
66  test JMJS 09.7.20 1873
65  test JMJS 09.7.20 1985
64  test JMJS 09.7.20 2184
63  test JMJS 09.7.20 2216
62  test JMJS 09.7.20 2118
61  VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§ JMJS 09.7.20 3907
60  test JMJS 09.7.20 1720
59  test JMJS 09.7.20 2027
58  test JMJS 09.7.20 1947
57  test JMJS 09.7.20 1911
56  test JMJS 09.7.20 1954
55  verilog Çаú »ùÇð­ÀÇ JMJS 16.5.30 2426
54  [verilog]create_generated_clock JMJS 15.4.28 2406
53  [Verilog]JDIFF JMJS 14.7.4 1776
52  [verilog]parameter definition JMJS 14.3.5 2061
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5000
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2679
49  Verdi JMJS 10.4.22 3544
48  draw hexa JMJS 10.4.9 2061
47  asfifo - Async FIFO JMJS 10.4.8 1920
46  VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡ JMJS 02.3.14 3590
45  synplify batch JMJS 10.3.8 2778
44  ÀüÀڽðè Type A JMJS 08.11.28 2276
43  I2C Webpage JMJS 08.2.25 2107
42  PC¿¡¼­ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog) JMJS 13.1.14 6233
41  [Verilog]vstring JMJS 17.9.27 2318
40  Riviera Simple Case JMJS 09.4.29 3412
39  [VHDL]DES Example JMJS 07.6.15 3265
38  [verilog]RAM example JMJS 09.6.5 3043
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2277
36  Jamie's VHDL Handbook JMJS 08.11.28 2963
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3547
34  RTL Job JMJS 09.4.29 2472
33  [VHDL]type example - package TYPES JMJS 06.2.2 1966
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9618
30  [verilog]array_module JMJS 05.12.8 2523
29  [verilog-2001]generate JMJS 05.12.8 3667
28  protected JMJS 05.11.18 2315
27  design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä? JMJS 09.7.20 3074
26  busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº? JMJS 04.11.9 2065
25  component¸¦ »ý¼ºÇؼ­ ´Ù¸¥ °÷¿¡¼­ È£ÃâÇÏ´Â ¹æ¹ý JMJS 04.11.4 2688
23  Array Of Array JMJS 04.8.16 2213
22  dumpfile, dumpvars JMJS 04.7.19 3900
21  Vending Machine Jamie 02.12.16 10334
20  Mini Vending Machine1 Jamie 02.12.10 7214
19  Mini Vending Machine Jamie 02.12.6 10048
18  Key Jamie 02.11.29 5234
17  Stop Watch Jamie 02.11.25 5806
16  Mealy Machine Jamie 02.8.29 6964
15  Moore Machine Jamie 02.8.29 18310
14  Up Down Counter Jamie 02.8.29 4332
13  Up Counter Jamie 02.8.29 3023
12  Edge Detecter Jamie 02.8.29 3233
11  Concept4 Jamie 02.8.28 2227
10  Concept3 Jamie 02.8.28 2302
9  Concept2_1 Jamie 02.8.28 2198
8  Concept2 Jamie 02.8.28 2284
7  Concept1 Jamie 02.8.26 2351
6  Tri State Buffer Jamie 02.8.26 3871
5  8x3 Encoder Jamie 02.8.28 4437
4  3x8 Decoder Jamie 02.8.28 4071
3  4bit Comparator Jamie 02.8.26 3450
2  °¡À§ ¹ÙÀ§ º¸ °ÔÀÓ Jamie 02.8.26 5645
1  Two Input Logic Jamie 02.8.26 2699
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