LogIn E-mail
설계이야기
Concept3
# 10 Jamie    02.8.28 16:39

1.Spec

이번에 설명할 concept은 data가 출력될 때의 clk의 순위입니다.
Block Diagram에서 보듯이 con signal에 선택된 입력 data가 clk의 상승 trigger에서
출력됩니다.
이것은 나중에 공부할 flip flop과 관련된 아주 중요한 개념이지요.
source와 block diagram을 비교하면서 공부하세요.

2.Input/Output



3.Timing



4.Block Diagram



5.RTL Code : concept3.vhd
  Test Vector : concept_tb.vhd

게시물: 93 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
95  draw_hexa.v JMJS 10.6.17 1819
94  jmjsxram3.v JMJS 10.4.9 1595
93  Verilog document JMJS 11.1.24 2150
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1744
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3170
90  gtkwave PC version JMJS 09.3.30 1571
89  ncsim option example JMJS 08.12.1 3818
88  [영상]keywords for web search JMJS 08.12.1 1554
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 5772
86  ncverilog option example JMJS 10.6.8 7012
85  [Verilog]Latch example JMJS 08.12.1 2166
84  Pad verilog example JMJS 01.3.16 4029
83  [ModelSim] vector JMJS 01.3.16 1763
82  RTL Code 분석순서 JMJS 09.4.29 2035
81  [temp]PIPE JMJS 08.10.2 1459
80  [temp]always-forever 무한루프 JMJS 08.10.2 1503
79  YCbCr2RGB.v JMJS 10.5.12 1700
78  [VHDL]rom64x8 JMJS 09.3.27 1332
77  [function]vector_compare JMJS 02.6.19 1277
76  [function]vector2integer JMJS 02.6.19 1377
75  [VHDL]ram8x4x8 JMJS 08.12.1 1261
74  [예]shift JMJS 02.6.19 1577
73  test JMJS 09.7.20 1355
72  test JMJS 09.7.20 1209
71  test JMJS 09.7.20 1121
70  test JMJS 09.7.20 1257
69  test JMJS 09.7.20 1268
68  test JMJS 09.7.20 1185
67  test JMJS 09.7.20 1109
66  test JMJS 09.7.20 1084
65  test JMJS 09.7.20 1181
64  test JMJS 09.7.20 1348
63  test JMJS 09.7.20 1344
62  test JMJS 09.7.20 1271
61  VHDL의 연산자 우선순위 JMJS 09.7.20 2941
60  test JMJS 09.7.20 1097
59  test JMJS 09.7.20 1188
58  test JMJS 09.7.20 1191
57  test JMJS 09.7.20 1135
56  test JMJS 09.7.20 1213
55  verilog 학과 샘플강의 JMJS 16.5.30 1592
54  [verilog]create_generated_clock JMJS 15.4.28 1650
53  [Verilog]JDIFF JMJS 14.7.4 1076
52  [verilog]parameter definition JMJS 14.3.5 1338
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4000
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2003
49  Verdi JMJS 10.4.22 2543
48  draw hexa JMJS 10.4.9 1398
47  asfifo - Async FIFO JMJS 10.4.8 1237
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 2816
45  synplify batch JMJS 10.3.8 1955
44  전자시계 Type A JMJS 08.11.28 1459
43  I2C Webpage JMJS 08.2.25 1363
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5092
41  [Verilog]vstring JMJS 17.9.27 1623
40  Riviera Simple Case JMJS 09.4.29 2627
39  [VHDL]DES Example JMJS 07.6.15 2481
38  [verilog]RAM example JMJS 09.6.5 2234
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1542
36  Jamie's VHDL Handbook JMJS 08.11.28 2159
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2782
34  RTL Job JMJS 09.4.29 1636
33  [VHDL]type example - package TYPES JMJS 06.2.2 1327
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 8406
30  [verilog]array_module JMJS 05.12.8 1652
29  [verilog-2001]generate JMJS 05.12.8 2878
28  protected JMJS 05.11.18 1504
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2321
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1454
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 1934
23  Array Of Array JMJS 04.8.16 1541
22  dumpfile, dumpvars JMJS 04.7.19 3046
21  Vending Machine Jamie 02.12.16 9317
20  Mini Vending Machine1 Jamie 02.12.10 6219
19  Mini Vending Machine Jamie 02.12.6 8908
18  Key Jamie 02.11.29 4354
17  Stop Watch Jamie 02.11.25 5104
16  Mealy Machine Jamie 02.8.29 5836
15  Moore Machine Jamie 02.8.29 15889
14  Up Down Counter Jamie 02.8.29 3407
13  Up Counter Jamie 02.8.29 2267
12  Edge Detecter Jamie 02.8.29 2398
11  Concept4 Jamie 02.8.28 1593
10  Concept3 Jamie 02.8.28 1582
9  Concept2_1 Jamie 02.8.28 1466
8  Concept2 Jamie 02.8.28 1553
7  Concept1 Jamie 02.8.26 1749
6  Tri State Buffer Jamie 02.8.26 3008
5  8x3 Encoder Jamie 02.8.28 3492
4  3x8 Decoder Jamie 02.8.28 3222
3  4bit Comparator Jamie 02.8.26 2659
2  가위 바위 보 게임 Jamie 02.8.26 4812
1  Two Input Logic Jamie 02.8.26 1989
[1]