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test
# 73 JMJS    09.7.20 15:57

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 238
97  test plusargs value plusargs JMJS 24.9.5 288
96  color text JMJS 24.7.13 292
95  draw_hexa.v JMJS 10.6.17 2498
94  jmjsxram3.v JMJS 10.4.9 2257
93  Verilog document JMJS 11.1.24 2869
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2458
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3878
90  gtkwave PC version JMJS 09.3.30 2218
89  ncsim option example JMJS 08.12.1 4602
88  [영상]keywords for web search JMJS 08.12.1 2226
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6484
86  ncverilog option example JMJS 10.6.8 8067
85  [Verilog]Latch example JMJS 08.12.1 2815
84  Pad verilog example JMJS 01.3.16 4724
83  [ModelSim] vector JMJS 01.3.16 2423
82  RTL Code 분석순서 JMJS 09.4.29 2709
81  [temp]PIPE JMJS 08.10.2 2076
80  [temp]always-forever 무한루프 JMJS 08.10.2 2170
79  YCbCr2RGB.v JMJS 10.5.12 2358
78  [VHDL]rom64x8 JMJS 09.3.27 1950
77  [function]vector_compare JMJS 02.6.19 1859
76  [function]vector2integer JMJS 02.6.19 1986
75  [VHDL]ram8x4x8 JMJS 08.12.1 1839
74  [예]shift JMJS 02.6.19 2242
73  test JMJS 09.7.20 2033
72  test JMJS 09.7.20 1752
71  test JMJS 09.7.20 1745
70  test JMJS 09.7.20 1837
69  test JMJS 09.7.20 1885
68  test JMJS 09.7.20 1829
67  test JMJS 09.7.20 1749
66  test JMJS 09.7.20 1729
65  test JMJS 09.7.20 1820
64  test JMJS 09.7.20 2029
63  test JMJS 09.7.20 2046
62  test JMJS 09.7.20 1971
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3767
60  test JMJS 09.7.20 1683
59  test JMJS 09.7.20 1840
58  test JMJS 09.7.20 1813
57  test JMJS 09.7.20 1767
56  test JMJS 09.7.20 1822
55  verilog 학과 샘플강의 JMJS 16.5.30 2371
54  [verilog]create_generated_clock JMJS 15.4.28 2344
53  [Verilog]JDIFF JMJS 14.7.4 1618
52  [verilog]parameter definition JMJS 14.3.5 1920
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4873
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2609
49  Verdi JMJS 10.4.22 3379
48  draw hexa JMJS 10.4.9 1970
47  asfifo - Async FIFO JMJS 10.4.8 1834
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3489
45  synplify batch JMJS 10.3.8 2600
44  전자시계 Type A JMJS 08.11.28 2120
43  I2C Webpage JMJS 08.2.25 1960
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6110
41  [Verilog]vstring JMJS 17.9.27 2185
40  Riviera Simple Case JMJS 09.4.29 3307
39  [VHDL]DES Example JMJS 07.6.15 3102
38  [verilog]RAM example JMJS 09.6.5 2863
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2147
36  Jamie's VHDL Handbook JMJS 08.11.28 2810
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3427
34  RTL Job JMJS 09.4.29 2275
33  [VHDL]type example - package TYPES JMJS 06.2.2 1895
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9477
30  [verilog]array_module JMJS 05.12.8 2404
29  [verilog-2001]generate JMJS 05.12.8 3509
28  protected JMJS 05.11.18 2170
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2968
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1952
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2593
23  Array Of Array JMJS 04.8.16 2107
22  dumpfile, dumpvars JMJS 04.7.19 3733
21  Vending Machine Jamie 02.12.16 10191
20  Mini Vending Machine1 Jamie 02.12.10 7075
19  Mini Vending Machine Jamie 02.12.6 9931
18  Key Jamie 02.11.29 5088
17  Stop Watch Jamie 02.11.25 5738
16  Mealy Machine Jamie 02.8.29 6837
15  Moore Machine Jamie 02.8.29 18141
14  Up Down Counter Jamie 02.8.29 4178
13  Up Counter Jamie 02.8.29 2866
12  Edge Detecter Jamie 02.8.29 3096
11  Concept4 Jamie 02.8.28 2162
10  Concept3 Jamie 02.8.28 2186
9  Concept2_1 Jamie 02.8.28 2068
8  Concept2 Jamie 02.8.28 2162
7  Concept1 Jamie 02.8.26 2316
6  Tri State Buffer Jamie 02.8.26 3668
5  8x3 Encoder Jamie 02.8.28 4289
4  3x8 Decoder Jamie 02.8.28 3944
3  4bit Comparator Jamie 02.8.26 3322
2  가위 바위 보 게임 Jamie 02.8.26 5610
1  Two Input Logic Jamie 02.8.26 2572
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