LogIn E-mail
설계이야기
Two Input Logic
# 1 Jamie    02.8.26 23:00

1.Spec

2 input logic회로를 설계해 봅시다.
출력은 입력의 and와 or 그리고 각 입력의 not을 출력하는 logic입니다.

2.Input/Output



3.RTL Code : two_input.vhd
  Test Vector : two_input_tb.vhd

게시물: 93 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
95  draw_hexa.v JMJS 10.6.17 1892
94  jmjsxram3.v JMJS 10.4.9 1678
93  Verilog document JMJS 11.1.24 2241
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1813
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3258
90  gtkwave PC version JMJS 09.3.30 1639
89  ncsim option example JMJS 08.12.1 3952
88  [영상]keywords for web search JMJS 08.12.1 1624
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 5897
86  ncverilog option example JMJS 10.6.8 7229
85  [Verilog]Latch example JMJS 08.12.1 2252
84  Pad verilog example JMJS 01.3.16 4135
83  [ModelSim] vector JMJS 01.3.16 1832
82  RTL Code 분석순서 JMJS 09.4.29 2120
81  [temp]PIPE JMJS 08.10.2 1526
80  [temp]always-forever 무한루프 JMJS 08.10.2 1577
79  YCbCr2RGB.v JMJS 10.5.12 1776
78  [VHDL]rom64x8 JMJS 09.3.27 1395
77  [function]vector_compare JMJS 02.6.19 1344
76  [function]vector2integer JMJS 02.6.19 1447
75  [VHDL]ram8x4x8 JMJS 08.12.1 1328
74  [예]shift JMJS 02.6.19 1645
73  test JMJS 09.7.20 1433
72  test JMJS 09.7.20 1267
71  test JMJS 09.7.20 1192
70  test JMJS 09.7.20 1321
69  test JMJS 09.7.20 1340
68  test JMJS 09.7.20 1253
67  test JMJS 09.7.20 1168
66  test JMJS 09.7.20 1148
65  test JMJS 09.7.20 1253
64  test JMJS 09.7.20 1483
63  test JMJS 09.7.20 1471
62  test JMJS 09.7.20 1397
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3143
60  test JMJS 09.7.20 1174
59  test JMJS 09.7.20 1258
58  test JMJS 09.7.20 1276
57  test JMJS 09.7.20 1205
56  test JMJS 09.7.20 1278
55  verilog 학과 샘플강의 JMJS 16.5.30 1821
54  [verilog]create_generated_clock JMJS 15.4.28 1810
53  [Verilog]JDIFF JMJS 14.7.4 1142
52  [verilog]parameter definition JMJS 14.3.5 1402
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4236
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2088
49  Verdi JMJS 10.4.22 2646
48  draw hexa JMJS 10.4.9 1474
47  asfifo - Async FIFO JMJS 10.4.8 1301
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 2911
45  synplify batch JMJS 10.3.8 2041
44  전자시계 Type A JMJS 08.11.28 1558
43  I2C Webpage JMJS 08.2.25 1416
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5371
41  [Verilog]vstring JMJS 17.9.27 1671
40  Riviera Simple Case JMJS 09.4.29 2768
39  [VHDL]DES Example JMJS 07.6.15 2535
38  [verilog]RAM example JMJS 09.6.5 2314
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1596
36  Jamie's VHDL Handbook JMJS 08.11.28 2220
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2843
34  RTL Job JMJS 09.4.29 1696
33  [VHDL]type example - package TYPES JMJS 06.2.2 1383
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 8785
30  [verilog]array_module JMJS 05.12.8 1745
29  [verilog-2001]generate JMJS 05.12.8 2951
28  protected JMJS 05.11.18 1583
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2417
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1512
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2016
23  Array Of Array JMJS 04.8.16 1594
22  dumpfile, dumpvars JMJS 04.7.19 3185
21  Vending Machine Jamie 02.12.16 9580
20  Mini Vending Machine1 Jamie 02.12.10 6415
19  Mini Vending Machine Jamie 02.12.6 9235
18  Key Jamie 02.11.29 4528
17  Stop Watch Jamie 02.11.25 5274
16  Mealy Machine Jamie 02.8.29 6109
15  Moore Machine Jamie 02.8.29 16437
14  Up Down Counter Jamie 02.8.29 3544
13  Up Counter Jamie 02.8.29 2334
12  Edge Detecter Jamie 02.8.29 2505
11  Concept4 Jamie 02.8.28 1661
10  Concept3 Jamie 02.8.28 1656
9  Concept2_1 Jamie 02.8.28 1520
8  Concept2 Jamie 02.8.28 1612
7  Concept1 Jamie 02.8.26 1805
6  Tri State Buffer Jamie 02.8.26 3084
5  8x3 Encoder Jamie 02.8.28 3672
4  3x8 Decoder Jamie 02.8.28 3353
3  4bit Comparator Jamie 02.8.26 2776
2  가위 바위 보 게임 Jamie 02.8.26 5085
1  Two Input Logic Jamie 02.8.26 2056
[1]