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test
# 59 JMJS    09.7.20 15:59

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 299
97  test plusargs value plusargs JMJS 24.9.5 335
96  color text JMJS 24.7.13 361
95  draw_hexa.v JMJS 10.6.17 2530
94  jmjsxram3.v JMJS 10.4.9 2377
93  Verilog document JMJS 11.1.24 2981
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2559
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3984
90  gtkwave PC version JMJS 09.3.30 2355
89  ncsim option example JMJS 08.12.1 4729
88  [영상]keywords for web search JMJS 08.12.1 2327
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6532
86  ncverilog option example JMJS 10.6.8 8184
85  [Verilog]Latch example JMJS 08.12.1 2923
84  Pad verilog example JMJS 01.3.16 4870
83  [ModelSim] vector JMJS 01.3.16 2540
82  RTL Code 분석순서 JMJS 09.4.29 2813
81  [temp]PIPE JMJS 08.10.2 2199
80  [temp]always-forever 무한루프 JMJS 08.10.2 2280
79  YCbCr2RGB.v JMJS 10.5.12 2473
78  [VHDL]rom64x8 JMJS 09.3.27 2038
77  [function]vector_compare JMJS 02.6.19 1938
76  [function]vector2integer JMJS 02.6.19 2122
75  [VHDL]ram8x4x8 JMJS 08.12.1 1900
74  [예]shift JMJS 02.6.19 2325
73  test JMJS 09.7.20 2154
72  test JMJS 09.7.20 1780
71  test JMJS 09.7.20 1875
70  test JMJS 09.7.20 1969
69  test JMJS 09.7.20 2013
68  test JMJS 09.7.20 1946
67  test JMJS 09.7.20 1882
66  test JMJS 09.7.20 1832
65  test JMJS 09.7.20 1936
64  test JMJS 09.7.20 2143
63  test JMJS 09.7.20 2176
62  test JMJS 09.7.20 2086
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3870
60  test JMJS 09.7.20 1718
59  test JMJS 09.7.20 1980
58  test JMJS 09.7.20 1914
57  test JMJS 09.7.20 1877
56  test JMJS 09.7.20 1920
55  verilog 학과 샘플강의 JMJS 16.5.30 2421
54  [verilog]create_generated_clock JMJS 15.4.28 2391
53  [Verilog]JDIFF JMJS 14.7.4 1730
52  [verilog]parameter definition JMJS 14.3.5 2028
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4961
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2662
49  Verdi JMJS 10.4.22 3496
48  draw hexa JMJS 10.4.9 2035
47  asfifo - Async FIFO JMJS 10.4.8 1904
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3576
45  synplify batch JMJS 10.3.8 2728
44  전자시계 Type A JMJS 08.11.28 2241
43  I2C Webpage JMJS 08.2.25 2075
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6218
41  [Verilog]vstring JMJS 17.9.27 2289
40  Riviera Simple Case JMJS 09.4.29 3377
39  [VHDL]DES Example JMJS 07.6.15 3224
38  [verilog]RAM example JMJS 09.6.5 2997
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2253
36  Jamie's VHDL Handbook JMJS 08.11.28 2914
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3517
34  RTL Job JMJS 09.4.29 2425
33  [VHDL]type example - package TYPES JMJS 06.2.2 1953
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9585
30  [verilog]array_module JMJS 05.12.8 2481
29  [verilog-2001]generate JMJS 05.12.8 3616
28  protected JMJS 05.11.18 2274
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3045
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2044
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2660
23  Array Of Array JMJS 04.8.16 2185
22  dumpfile, dumpvars JMJS 04.7.19 3854
21  Vending Machine Jamie 02.12.16 10296
20  Mini Vending Machine1 Jamie 02.12.10 7175
19  Mini Vending Machine Jamie 02.12.6 10021
18  Key Jamie 02.11.29 5192
17  Stop Watch Jamie 02.11.25 5795
16  Mealy Machine Jamie 02.8.29 6935
15  Moore Machine Jamie 02.8.29 18274
14  Up Down Counter Jamie 02.8.29 4292
13  Up Counter Jamie 02.8.29 2987
12  Edge Detecter Jamie 02.8.29 3203
11  Concept4 Jamie 02.8.28 2217
10  Concept3 Jamie 02.8.28 2277
9  Concept2_1 Jamie 02.8.28 2169
8  Concept2 Jamie 02.8.28 2257
7  Concept1 Jamie 02.8.26 2346
6  Tri State Buffer Jamie 02.8.26 3817
5  8x3 Encoder Jamie 02.8.28 4413
4  3x8 Decoder Jamie 02.8.28 4039
3  4bit Comparator Jamie 02.8.26 3427
2  가위 바위 보 게임 Jamie 02.8.26 5641
1  Two Input Logic Jamie 02.8.26 2668
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