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test
# 59 JMJS    09.7.20 15:59

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 342
97  test plusargs value plusargs JMJS 24.9.5 355
96  color text JMJS 24.7.13 402
95  draw_hexa.v JMJS 10.6.17 2553
94  jmjsxram3.v JMJS 10.4.9 2488
93  Verilog document JMJS 11.1.24 3078
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2674
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4116
90  gtkwave PC version JMJS 09.3.30 2500
89  ncsim option example JMJS 08.12.1 4851
88  [영상]keywords for web search JMJS 08.12.1 2455
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6560
86  ncverilog option example JMJS 10.6.8 8305
85  [Verilog]Latch example JMJS 08.12.1 3044
84  Pad verilog example JMJS 01.3.16 4994
83  [ModelSim] vector JMJS 01.3.16 2678
82  RTL Code 분석순서 JMJS 09.4.29 2917
81  [temp]PIPE JMJS 08.10.2 2323
80  [temp]always-forever 무한루프 JMJS 08.10.2 2402
79  YCbCr2RGB.v JMJS 10.5.12 2578
78  [VHDL]rom64x8 JMJS 09.3.27 2124
77  [function]vector_compare JMJS 02.6.19 2003
76  [function]vector2integer JMJS 02.6.19 2245
75  [VHDL]ram8x4x8 JMJS 08.12.1 1949
74  [예]shift JMJS 02.6.19 2425
73  test JMJS 09.7.20 2282
72  test JMJS 09.7.20 1801
71  test JMJS 09.7.20 2003
70  test JMJS 09.7.20 2086
69  test JMJS 09.7.20 2139
68  test JMJS 09.7.20 2079
67  test JMJS 09.7.20 2012
66  test JMJS 09.7.20 1953
65  test JMJS 09.7.20 2080
64  test JMJS 09.7.20 2261
63  test JMJS 09.7.20 2314
62  test JMJS 09.7.20 2187
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3971
60  test JMJS 09.7.20 1730
59  test JMJS 09.7.20 2120
58  test JMJS 09.7.20 2032
57  test JMJS 09.7.20 1990
56  test JMJS 09.7.20 2035
55  verilog 학과 샘플강의 JMJS 16.5.30 2440
54  [verilog]create_generated_clock JMJS 15.4.28 2436
53  [Verilog]JDIFF JMJS 14.7.4 1872
52  [verilog]parameter definition JMJS 14.3.5 2141
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5086
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2707
49  Verdi JMJS 10.4.22 3633
48  draw hexa JMJS 10.4.9 2098
47  asfifo - Async FIFO JMJS 10.4.8 1961
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3648
45  synplify batch JMJS 10.3.8 2857
44  전자시계 Type A JMJS 08.11.28 2363
43  I2C Webpage JMJS 08.2.25 2183
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6256
41  [Verilog]vstring JMJS 17.9.27 2377
40  Riviera Simple Case JMJS 09.4.29 3462
39  [VHDL]DES Example JMJS 07.6.15 3353
38  [verilog]RAM example JMJS 09.6.5 3116
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2356
36  Jamie's VHDL Handbook JMJS 08.11.28 3052
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3636
34  RTL Job JMJS 09.4.29 2570
33  [VHDL]type example - package TYPES JMJS 06.2.2 1989
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9687
30  [verilog]array_module JMJS 05.12.8 2589
29  [verilog-2001]generate JMJS 05.12.8 3737
28  protected JMJS 05.11.18 2411
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3121
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2100
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2735
23  Array Of Array JMJS 04.8.16 2277
22  dumpfile, dumpvars JMJS 04.7.19 3979
21  Vending Machine Jamie 02.12.16 10418
20  Mini Vending Machine1 Jamie 02.12.10 7274
19  Mini Vending Machine Jamie 02.12.6 10104
18  Key Jamie 02.11.29 5316
17  Stop Watch Jamie 02.11.25 5831
16  Mealy Machine Jamie 02.8.29 7041
15  Moore Machine Jamie 02.8.29 18375
14  Up Down Counter Jamie 02.8.29 4414
13  Up Counter Jamie 02.8.29 3110
12  Edge Detecter Jamie 02.8.29 3317
11  Concept4 Jamie 02.8.28 2245
10  Concept3 Jamie 02.8.28 2377
9  Concept2_1 Jamie 02.8.28 2268
8  Concept2 Jamie 02.8.28 2354
7  Concept1 Jamie 02.8.26 2362
6  Tri State Buffer Jamie 02.8.26 3966
5  8x3 Encoder Jamie 02.8.28 4513
4  3x8 Decoder Jamie 02.8.28 4142
3  4bit Comparator Jamie 02.8.26 3523
2  가위 바위 보 게임 Jamie 02.8.26 5656
1  Two Input Logic Jamie 02.8.26 2782
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