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59
JMJS
09.7.20 15:59
test
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interface
JMJS
25.1.20
67
97
test plusargs value plusargs
JMJS
24.9.5
135
96
color text
JMJS
24.7.13
142
95
draw_hexa.v
JMJS
10.6.17
2346
94
jmjsxram3.v
JMJS
10.4.9
2076
93
Verilog document
JMJS
11.1.24
2663
92
[verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3;
JMJS
09.3.31
2216
91
[verilog]forever, repeat, strobe, realtime, ...
JMJS
09.7.6
3700
90
gtkwave PC version
JMJS
09.3.30
2019
89
ncsim option example
JMJS
08.12.1
4401
88
[¿µ»ó]keywords for web search
JMJS
08.12.1
2021
87
[Verilog]fdisplay fopen fscanf
JMJS
11.1.24
6352
86
ncverilog option example
JMJS
10.6.8
7827
85
[Verilog]Latch example
JMJS
08.12.1
2635
84
Pad verilog example
JMJS
01.3.16
4554
83
[ModelSim] vector
JMJS
01.3.16
2231
82
RTL Code ºÐ¼®¼ø¼
JMJS
09.4.29
2526
81
[temp]PIPE
JMJS
08.10.2
1889
80
[temp]always-forever ¹«ÇÑ·çÇÁ
JMJS
08.10.2
1974
79
YCbCr2RGB.v
JMJS
10.5.12
2177
78
[VHDL]rom64x8
JMJS
09.3.27
1789
77
[function]vector_compare
JMJS
02.6.19
1746
76
[function]vector2integer
JMJS
02.6.19
1811
75
[VHDL]ram8x4x8
JMJS
08.12.1
1702
74
[¿¹]shift
JMJS
02.6.19
2049
73
test
JMJS
09.7.20
1855
72
test
JMJS
09.7.20
1639
71
test
JMJS
09.7.20
1571
70
test
JMJS
09.7.20
1667
69
test
JMJS
09.7.20
1701
68
test
JMJS
09.7.20
1634
67
test
JMJS
09.7.20
1562
66
test
JMJS
09.7.20
1511
65
test
JMJS
09.7.20
1633
64
test
JMJS
09.7.20
1864
63
test
JMJS
09.7.20
1867
62
test
JMJS
09.7.20
1786
61
VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§
JMJS
09.7.20
3587
60
test
JMJS
09.7.20
1572
59
test
JMJS
09.7.20
1658
58
test
JMJS
09.7.20
1639
57
test
JMJS
09.7.20
1578
56
test
JMJS
09.7.20
1626
55
verilog Çаú »ùÇðÀÇ
JMJS
16.5.30
2243
54
[verilog]create_generated_clock
JMJS
15.4.28
2231
53
[Verilog]JDIFF
JMJS
14.7.4
1488
52
[verilog]parameter definition
JMJS
14.3.5
1762
51
[verilog]sformat fopen fscanf fwrite fclose
JMJS
12.1.31
4720
50
Verilog File I/0,Verilog file handling
JMJS
12.1.30
2490
49
Verdi
JMJS
10.4.22
3159
48
draw hexa
JMJS
10.4.9
1831
47
asfifo - Async FIFO
JMJS
10.4.8
1660
46
VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡
JMJS
02.3.14
3315
45
synplify batch
JMJS
10.3.8
2418
44
ÀüÀڽðè Type A
JMJS
08.11.28
1934
43
I2C Webpage
JMJS
08.2.25
1781
42
PC¿¡¼ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog)
JMJS
13.1.14
5942
41
[Verilog]vstring
JMJS
17.9.27
2018
40
Riviera Simple Case
JMJS
09.4.29
3159
39
[VHDL]DES Example
JMJS
07.6.15
2913
38
[verilog]RAM example
JMJS
09.6.5
2680
37
ROM example [VerilogHDL, RTL]
JMJS
04.5.27
1953
36
Jamie's VHDL Handbook
JMJS
08.11.28
2615
35
Dualport RAM example [VerilogHDL, RTL]
JMJS
04.5.27
3259
34
RTL Job
JMJS
09.4.29
2091
33
[VHDL]type example - package TYPES
JMJS
06.2.2
1773
32
[verilog]`define `ifdef `elsif `else `endif ...
JMJS
10.5.11
9295
30
[verilog]array_module
JMJS
05.12.8
2231
29
[verilog-2001]generate
JMJS
05.12.8
3331
28
protected
JMJS
05.11.18
1993
27
design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä?
JMJS
09.7.20
2803
26
busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº?
JMJS
04.11.9
1839
25
component¸¦ »ý¼ºÇؼ ´Ù¸¥ °÷¿¡¼ È£ÃâÇÏ´Â ¹æ¹ý
JMJS
04.11.4
2419
23
Array Of Array
JMJS
04.8.16
1932
22
dumpfile, dumpvars
JMJS
04.7.19
3551
21
Vending Machine
Jamie
02.12.16
10023
20
Mini Vending Machine1
Jamie
02.12.10
6890
19
Mini Vending Machine
Jamie
02.12.6
9694
18
Key
Jamie
02.11.29
4919
17
Stop Watch
Jamie
02.11.25
5626
16
Mealy Machine
Jamie
02.8.29
6672
15
Moore Machine
Jamie
02.8.29
17860
14
Up Down Counter
Jamie
02.8.29
4002
13
Up Counter
Jamie
02.8.29
2710
12
Edge Detecter
Jamie
02.8.29
2907
11
Concept4
Jamie
02.8.28
2058
10
Concept3
Jamie
02.8.28
2002
9
Concept2_1
Jamie
02.8.28
1892
8
Concept2
Jamie
02.8.28
1959
7
Concept1
Jamie
02.8.26
2169
6
Tri State Buffer
Jamie
02.8.26
3480
5
8x3 Encoder
Jamie
02.8.28
4084
4
3x8 Decoder
Jamie
02.8.28
3767
3
4bit Comparator
Jamie
02.8.26
3152
2
°¡À§ ¹ÙÀ§ º¸ °ÔÀÓ
Jamie
02.8.26
5503
1
Two Input Logic
Jamie
02.8.26
2406
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