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Riviera Simple Case
# 40 JMJS    09.4.29 07:34

%cat riviera.env
setenv LD_LIBRARY_PATH $LD_LIBRARY_PATH:riviera/bin
set path ($path riviera riviera/bin)

%cat script
vlib work
set worklib work
vmap work work
vlog -f run.f
vsim system -do full.do
#vsim system -do fsdb.do

%cat full.do
$fsdbDumpfile full.fsdb
$fsdbDumpvars 0 system
run 50000ns
endsim
exit



Riviera - console commands

1.Change the Directory. //File => Change Directory or cd <Directory Path>
2.vlib work //work 라이브러리를 생성한다.
3.vmap work work
4.set worklib work // 작업 라이브러리 지정한다.
5.vlog -dbg -l <Library name>*.v //동일 폴더내의 모든 verilog 파일을 컴파일 한다.
6.adir //컴파일 하고 난 후 work library에 저장된 List를 보여준다
7.vsim +access +r top_level //top module을 Initialize할 수 있다.
8.$fsdbDumpfile test.fsdb
9.$fsdbDumpvars 0 top_level //Initialize 된 후에 Fsdbfile에 관련한 commands
10.run 100us
11.endsim

사용할 script
1. make library >> vlib work
2. set library >> set worklib work
3. mapping library >> vmap work work (logical to phsical)
4. compile >> vlog -f run.f
5. simulation >> vsim top

//(To fast simulation with SLP mode>>-o5

##### run_riv.sh #####
vlib work
set worklib work
vmap work work
vlog -f run.f > compile.log
vsim -o5 +access +r tb_top -do fsdb.do

##### fsdb.do #####
$fsdbDumpfile ./fsdb/test.fsdb
$fsdbDumpvars 0 tb_top
run 2000us
endsim
exit

Riviera - Library
#Linux Flattform
1. xilinx_verilog.tar.gz, xilinx_vhdl.tar.gz, xilinx_schematic.tar.gz을 ~vlib/ 폴더에 압축을 푼다.(gzip -dc xilinx_verilog.tar.gz|tar xvf -)
2. Vi library.cfg 파일을 vi 편집기로 연다.
3. Library를 추가한다.
첨부파일: riviera_simple_case.tgz
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 327
97  test plusargs value plusargs JMJS 24.9.5 346
96  color text JMJS 24.7.13 381
95  draw_hexa.v JMJS 10.6.17 2539
94  jmjsxram3.v JMJS 10.4.9 2429
93  Verilog document JMJS 11.1.24 3027
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2618
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4052
90  gtkwave PC version JMJS 09.3.30 2417
89  ncsim option example JMJS 08.12.1 4783
88  [영상]keywords for web search JMJS 08.12.1 2382
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6544
86  ncverilog option example JMJS 10.6.8 8241
85  [Verilog]Latch example JMJS 08.12.1 2983
84  Pad verilog example JMJS 01.3.16 4917
83  [ModelSim] vector JMJS 01.3.16 2608
82  RTL Code 분석순서 JMJS 09.4.29 2857
81  [temp]PIPE JMJS 08.10.2 2254
80  [temp]always-forever 무한루프 JMJS 08.10.2 2332
79  YCbCr2RGB.v JMJS 10.5.12 2529
78  [VHDL]rom64x8 JMJS 09.3.27 2076
77  [function]vector_compare JMJS 02.6.19 1978
76  [function]vector2integer JMJS 02.6.19 2181
75  [VHDL]ram8x4x8 JMJS 08.12.1 1916
74  [예]shift JMJS 02.6.19 2371
73  test JMJS 09.7.20 2214
72  test JMJS 09.7.20 1789
71  test JMJS 09.7.20 1928
70  test JMJS 09.7.20 2025
69  test JMJS 09.7.20 2070
68  test JMJS 09.7.20 2002
67  test JMJS 09.7.20 1940
66  test JMJS 09.7.20 1888
65  test JMJS 09.7.20 2007
64  test JMJS 09.7.20 2202
63  test JMJS 09.7.20 2236
62  test JMJS 09.7.20 2131
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3922
60  test JMJS 09.7.20 1722
59  test JMJS 09.7.20 2058
58  test JMJS 09.7.20 1965
57  test JMJS 09.7.20 1932
56  test JMJS 09.7.20 1971
55  verilog 학과 샘플강의 JMJS 16.5.30 2428
54  [verilog]create_generated_clock JMJS 15.4.28 2409
53  [Verilog]JDIFF JMJS 14.7.4 1794
52  [verilog]parameter definition JMJS 14.3.5 2082
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5018
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2684
49  Verdi JMJS 10.4.22 3561
48  draw hexa JMJS 10.4.9 2070
47  asfifo - Async FIFO JMJS 10.4.8 1934
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3606
45  synplify batch JMJS 10.3.8 2798
44  전자시계 Type A JMJS 08.11.28 2292
43  I2C Webpage JMJS 08.2.25 2127
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6239
41  [Verilog]vstring JMJS 17.9.27 2333
40  Riviera Simple Case JMJS 09.4.29 3427
39  [VHDL]DES Example JMJS 07.6.15 3279
38  [verilog]RAM example JMJS 09.6.5 3057
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2291
36  Jamie's VHDL Handbook JMJS 08.11.28 2986
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3565
34  RTL Job JMJS 09.4.29 2495
33  [VHDL]type example - package TYPES JMJS 06.2.2 1970
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9632
30  [verilog]array_module JMJS 05.12.8 2534
29  [verilog-2001]generate JMJS 05.12.8 3679
28  protected JMJS 05.11.18 2330
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3081
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2071
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2702
23  Array Of Array JMJS 04.8.16 2226
22  dumpfile, dumpvars JMJS 04.7.19 3918
21  Vending Machine Jamie 02.12.16 10356
20  Mini Vending Machine1 Jamie 02.12.10 7225
19  Mini Vending Machine Jamie 02.12.6 10059
18  Key Jamie 02.11.29 5256
17  Stop Watch Jamie 02.11.25 5810
16  Mealy Machine Jamie 02.8.29 6976
15  Moore Machine Jamie 02.8.29 18327
14  Up Down Counter Jamie 02.8.29 4347
13  Up Counter Jamie 02.8.29 3039
12  Edge Detecter Jamie 02.8.29 3251
11  Concept4 Jamie 02.8.28 2229
10  Concept3 Jamie 02.8.28 2317
9  Concept2_1 Jamie 02.8.28 2217
8  Concept2 Jamie 02.8.28 2301
7  Concept1 Jamie 02.8.26 2352
6  Tri State Buffer Jamie 02.8.26 3894
5  8x3 Encoder Jamie 02.8.28 4448
4  3x8 Decoder Jamie 02.8.28 4089
3  4bit Comparator Jamie 02.8.26 3469
2  가위 바위 보 게임 Jamie 02.8.26 5646
1  Two Input Logic Jamie 02.8.26 2718
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