LogIn E-mail
설계이야기
Riviera Simple Case
# 40 JMJS    09.4.29 07:34

%cat riviera.env
setenv LD_LIBRARY_PATH $LD_LIBRARY_PATH:riviera/bin
set path ($path riviera riviera/bin)

%cat script
vlib work
set worklib work
vmap work work
vlog -f run.f
vsim system -do full.do
#vsim system -do fsdb.do

%cat full.do
$fsdbDumpfile full.fsdb
$fsdbDumpvars 0 system
run 50000ns
endsim
exit



Riviera - console commands

1.Change the Directory. //File => Change Directory or cd <Directory Path>
2.vlib work //work 라이브러리를 생성한다.
3.vmap work work
4.set worklib work // 작업 라이브러리 지정한다.
5.vlog -dbg -l <Library name>*.v //동일 폴더내의 모든 verilog 파일을 컴파일 한다.
6.adir //컴파일 하고 난 후 work library에 저장된 List를 보여준다
7.vsim +access +r top_level //top module을 Initialize할 수 있다.
8.$fsdbDumpfile test.fsdb
9.$fsdbDumpvars 0 top_level //Initialize 된 후에 Fsdbfile에 관련한 commands
10.run 100us
11.endsim

사용할 script
1. make library >> vlib work
2. set library >> set worklib work
3. mapping library >> vmap work work (logical to phsical)
4. compile >> vlog -f run.f
5. simulation >> vsim top

//(To fast simulation with SLP mode>>-o5

##### run_riv.sh #####
vlib work
set worklib work
vmap work work
vlog -f run.f > compile.log
vsim -o5 +access +r tb_top -do fsdb.do

##### fsdb.do #####
$fsdbDumpfile ./fsdb/test.fsdb
$fsdbDumpvars 0 tb_top
run 2000us
endsim
exit

Riviera - Library
#Linux Flattform
1. xilinx_verilog.tar.gz, xilinx_vhdl.tar.gz, xilinx_schematic.tar.gz을 ~vlib/ 폴더에 압축을 푼다.(gzip -dc xilinx_verilog.tar.gz|tar xvf -)
2. Vi library.cfg 파일을 vi 편집기로 연다.
3. Library를 추가한다.

첨부파일: riviera_simple_case.tgz
게시물: 93 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
95  draw_hexa.v JMJS 10.6.17 2132
94  jmjsxram3.v JMJS 10.4.9 1868
93  Verilog document JMJS 11.1.24 2443
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2013
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3482
90  gtkwave PC version JMJS 09.3.30 1819
89  ncsim option example JMJS 08.12.1 4188
88  [영상]keywords for web search JMJS 08.12.1 1824
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6142
86  ncverilog option example JMJS 10.6.8 7562
85  [Verilog]Latch example JMJS 08.12.1 2432
84  Pad verilog example JMJS 01.3.16 4337
83  [ModelSim] vector JMJS 01.3.16 2031
82  RTL Code 분석순서 JMJS 09.4.29 2328
81  [temp]PIPE JMJS 08.10.2 1696
80  [temp]always-forever 무한루프 JMJS 08.10.2 1784
79  YCbCr2RGB.v JMJS 10.5.12 1980
78  [VHDL]rom64x8 JMJS 09.3.27 1584
77  [function]vector_compare JMJS 02.6.19 1553
76  [function]vector2integer JMJS 02.6.19 1624
75  [VHDL]ram8x4x8 JMJS 08.12.1 1504
74  [예]shift JMJS 02.6.19 1853
73  test JMJS 09.7.20 1640
72  test JMJS 09.7.20 1444
71  test JMJS 09.7.20 1375
70  test JMJS 09.7.20 1485
69  test JMJS 09.7.20 1511
68  test JMJS 09.7.20 1433
67  test JMJS 09.7.20 1359
66  test JMJS 09.7.20 1317
65  test JMJS 09.7.20 1424
64  test JMJS 09.7.20 1681
63  test JMJS 09.7.20 1673
62  test JMJS 09.7.20 1603
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3383
60  test JMJS 09.7.20 1376
59  test JMJS 09.7.20 1449
58  test JMJS 09.7.20 1456
57  test JMJS 09.7.20 1392
56  test JMJS 09.7.20 1442
55  verilog 학과 샘플강의 JMJS 16.5.30 2062
54  [verilog]create_generated_clock JMJS 15.4.28 2026
53  [Verilog]JDIFF JMJS 14.7.4 1309
52  [verilog]parameter definition JMJS 14.3.5 1577
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4527
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2291
49  Verdi JMJS 10.4.22 2896
48  draw hexa JMJS 10.4.9 1647
47  asfifo - Async FIFO JMJS 10.4.8 1479
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3112
45  synplify batch JMJS 10.3.8 2238
44  전자시계 Type A JMJS 08.11.28 1731
43  I2C Webpage JMJS 08.2.25 1596
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5736
41  [Verilog]vstring JMJS 17.9.27 1830
40  Riviera Simple Case JMJS 09.4.29 2976
39  [VHDL]DES Example JMJS 07.6.15 2718
38  [verilog]RAM example JMJS 09.6.5 2493
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1756
36  Jamie's VHDL Handbook JMJS 08.11.28 2414
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3038
34  RTL Job JMJS 09.4.29 1888
33  [VHDL]type example - package TYPES JMJS 06.2.2 1573
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9099
30  [verilog]array_module JMJS 05.12.8 1991
29  [verilog-2001]generate JMJS 05.12.8 3143
28  protected JMJS 05.11.18 1782
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2594
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1665
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2211
23  Array Of Array JMJS 04.8.16 1749
22  dumpfile, dumpvars JMJS 04.7.19 3371
21  Vending Machine Jamie 02.12.16 9829
20  Mini Vending Machine1 Jamie 02.12.10 6667
19  Mini Vending Machine Jamie 02.12.6 9480
18  Key Jamie 02.11.29 4719
17  Stop Watch Jamie 02.11.25 5452
16  Mealy Machine Jamie 02.8.29 6464
15  Moore Machine Jamie 02.8.29 17475
14  Up Down Counter Jamie 02.8.29 3779
13  Up Counter Jamie 02.8.29 2520
12  Edge Detecter Jamie 02.8.29 2713
11  Concept4 Jamie 02.8.28 1863
10  Concept3 Jamie 02.8.28 1812
9  Concept2_1 Jamie 02.8.28 1694
8  Concept2 Jamie 02.8.28 1766
7  Concept1 Jamie 02.8.26 1973
6  Tri State Buffer Jamie 02.8.26 3281
5  8x3 Encoder Jamie 02.8.28 3877
4  3x8 Decoder Jamie 02.8.28 3552
3  4bit Comparator Jamie 02.8.26 2946
2  가위 바위 보 게임 Jamie 02.8.26 5301
1  Two Input Logic Jamie 02.8.26 2216
[1]