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test
# 58 JMJS    09.7.20 16:00

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 300
97  test plusargs value plusargs JMJS 24.9.5 336
96  color text JMJS 24.7.13 364
95  draw_hexa.v JMJS 10.6.17 2531
94  jmjsxram3.v JMJS 10.4.9 2383
93  Verilog document JMJS 11.1.24 2985
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2565
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3989
90  gtkwave PC version JMJS 09.3.30 2364
89  ncsim option example JMJS 08.12.1 4732
88  [영상]keywords for web search JMJS 08.12.1 2334
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6535
86  ncverilog option example JMJS 10.6.8 8190
85  [Verilog]Latch example JMJS 08.12.1 2928
84  Pad verilog example JMJS 01.3.16 4875
83  [ModelSim] vector JMJS 01.3.16 2549
82  RTL Code 분석순서 JMJS 09.4.29 2817
81  [temp]PIPE JMJS 08.10.2 2206
80  [temp]always-forever 무한루프 JMJS 08.10.2 2286
79  YCbCr2RGB.v JMJS 10.5.12 2478
78  [VHDL]rom64x8 JMJS 09.3.27 2043
77  [function]vector_compare JMJS 02.6.19 1945
76  [function]vector2integer JMJS 02.6.19 2126
75  [VHDL]ram8x4x8 JMJS 08.12.1 1902
74  [예]shift JMJS 02.6.19 2330
73  test JMJS 09.7.20 2160
72  test JMJS 09.7.20 1781
71  test JMJS 09.7.20 1879
70  test JMJS 09.7.20 1972
69  test JMJS 09.7.20 2019
68  test JMJS 09.7.20 1950
67  test JMJS 09.7.20 1886
66  test JMJS 09.7.20 1839
65  test JMJS 09.7.20 1943
64  test JMJS 09.7.20 2148
63  test JMJS 09.7.20 2182
62  test JMJS 09.7.20 2092
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3876
60  test JMJS 09.7.20 1718
59  test JMJS 09.7.20 1987
58  test JMJS 09.7.20 1919
57  test JMJS 09.7.20 1883
56  test JMJS 09.7.20 1925
55  verilog 학과 샘플강의 JMJS 16.5.30 2421
54  [verilog]create_generated_clock JMJS 15.4.28 2393
53  [Verilog]JDIFF JMJS 14.7.4 1738
52  [verilog]parameter definition JMJS 14.3.5 2034
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4965
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2665
49  Verdi JMJS 10.4.22 3501
48  draw hexa JMJS 10.4.9 2039
47  asfifo - Async FIFO JMJS 10.4.8 1906
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3581
45  synplify batch JMJS 10.3.8 2733
44  전자시계 Type A JMJS 08.11.28 2242
43  I2C Webpage JMJS 08.2.25 2080
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6220
41  [Verilog]vstring JMJS 17.9.27 2294
40  Riviera Simple Case JMJS 09.4.29 3383
39  [VHDL]DES Example JMJS 07.6.15 3229
38  [verilog]RAM example JMJS 09.6.5 3007
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2257
36  Jamie's VHDL Handbook JMJS 08.11.28 2920
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3522
34  RTL Job JMJS 09.4.29 2430
33  [VHDL]type example - package TYPES JMJS 06.2.2 1955
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9591
30  [verilog]array_module JMJS 05.12.8 2484
29  [verilog-2001]generate JMJS 05.12.8 3623
28  protected JMJS 05.11.18 2283
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3052
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2049
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2664
23  Array Of Array JMJS 04.8.16 2191
22  dumpfile, dumpvars JMJS 04.7.19 3864
21  Vending Machine Jamie 02.12.16 10301
20  Mini Vending Machine1 Jamie 02.12.10 7178
19  Mini Vending Machine Jamie 02.12.6 10025
18  Key Jamie 02.11.29 5197
17  Stop Watch Jamie 02.11.25 5799
16  Mealy Machine Jamie 02.8.29 6942
15  Moore Machine Jamie 02.8.29 18280
14  Up Down Counter Jamie 02.8.29 4297
13  Up Counter Jamie 02.8.29 2993
12  Edge Detecter Jamie 02.8.29 3211
11  Concept4 Jamie 02.8.28 2219
10  Concept3 Jamie 02.8.28 2282
9  Concept2_1 Jamie 02.8.28 2170
8  Concept2 Jamie 02.8.28 2261
7  Concept1 Jamie 02.8.26 2347
6  Tri State Buffer Jamie 02.8.26 3822
5  8x3 Encoder Jamie 02.8.28 4417
4  3x8 Decoder Jamie 02.8.28 4041
3  4bit Comparator Jamie 02.8.26 3430
2  가위 바위 보 게임 Jamie 02.8.26 5643
1  Two Input Logic Jamie 02.8.26 2674
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