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test
# 58 JMJS    09.7.20 16:00

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 252
97  test plusargs value plusargs JMJS 24.9.5 298
96  color text JMJS 24.7.13 304
95  draw_hexa.v JMJS 10.6.17 2506
94  jmjsxram3.v JMJS 10.4.9 2277
93  Verilog document JMJS 11.1.24 2888
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2477
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3888
90  gtkwave PC version JMJS 09.3.30 2240
89  ncsim option example JMJS 08.12.1 4618
88  [영상]keywords for web search JMJS 08.12.1 2249
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6493
86  ncverilog option example JMJS 10.6.8 8082
85  [Verilog]Latch example JMJS 08.12.1 2833
84  Pad verilog example JMJS 01.3.16 4742
83  [ModelSim] vector JMJS 01.3.16 2438
82  RTL Code 분석순서 JMJS 09.4.29 2723
81  [temp]PIPE JMJS 08.10.2 2093
80  [temp]always-forever 무한루프 JMJS 08.10.2 2188
79  YCbCr2RGB.v JMJS 10.5.12 2377
78  [VHDL]rom64x8 JMJS 09.3.27 1964
77  [function]vector_compare JMJS 02.6.19 1870
76  [function]vector2integer JMJS 02.6.19 2000
75  [VHDL]ram8x4x8 JMJS 08.12.1 1847
74  [예]shift JMJS 02.6.19 2257
73  test JMJS 09.7.20 2053
72  test JMJS 09.7.20 1757
71  test JMJS 09.7.20 1762
70  test JMJS 09.7.20 1855
69  test JMJS 09.7.20 1902
68  test JMJS 09.7.20 1847
67  test JMJS 09.7.20 1767
66  test JMJS 09.7.20 1746
65  test JMJS 09.7.20 1838
64  test JMJS 09.7.20 2050
63  test JMJS 09.7.20 2061
62  test JMJS 09.7.20 1984
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3791
60  test JMJS 09.7.20 1690
59  test JMJS 09.7.20 1852
58  test JMJS 09.7.20 1829
57  test JMJS 09.7.20 1785
56  test JMJS 09.7.20 1839
55  verilog 학과 샘플강의 JMJS 16.5.30 2383
54  [verilog]create_generated_clock JMJS 15.4.28 2353
53  [Verilog]JDIFF JMJS 14.7.4 1627
52  [verilog]parameter definition JMJS 14.3.5 1937
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4892
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2618
49  Verdi JMJS 10.4.22 3396
48  draw hexa JMJS 10.4.9 1982
47  asfifo - Async FIFO JMJS 10.4.8 1845
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3504
45  synplify batch JMJS 10.3.8 2616
44  전자시계 Type A JMJS 08.11.28 2139
43  I2C Webpage JMJS 08.2.25 1973
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6130
41  [Verilog]vstring JMJS 17.9.27 2205
40  Riviera Simple Case JMJS 09.4.29 3318
39  [VHDL]DES Example JMJS 07.6.15 3125
38  [verilog]RAM example JMJS 09.6.5 2886
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2165
36  Jamie's VHDL Handbook JMJS 08.11.28 2827
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3443
34  RTL Job JMJS 09.4.29 2294
33  [VHDL]type example - package TYPES JMJS 06.2.2 1906
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9495
30  [verilog]array_module JMJS 05.12.8 2416
29  [verilog-2001]generate JMJS 05.12.8 3522
28  protected JMJS 05.11.18 2183
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2981
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1960
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2608
23  Array Of Array JMJS 04.8.16 2127
22  dumpfile, dumpvars JMJS 04.7.19 3748
21  Vending Machine Jamie 02.12.16 10206
20  Mini Vending Machine1 Jamie 02.12.10 7088
19  Mini Vending Machine Jamie 02.12.6 9939
18  Key Jamie 02.11.29 5107
17  Stop Watch Jamie 02.11.25 5746
16  Mealy Machine Jamie 02.8.29 6856
15  Moore Machine Jamie 02.8.29 18163
14  Up Down Counter Jamie 02.8.29 4197
13  Up Counter Jamie 02.8.29 2883
12  Edge Detecter Jamie 02.8.29 3114
11  Concept4 Jamie 02.8.28 2169
10  Concept3 Jamie 02.8.28 2198
9  Concept2_1 Jamie 02.8.28 2085
8  Concept2 Jamie 02.8.28 2176
7  Concept1 Jamie 02.8.26 2326
6  Tri State Buffer Jamie 02.8.26 3685
5  8x3 Encoder Jamie 02.8.28 4302
4  3x8 Decoder Jamie 02.8.28 3960
3  4bit Comparator Jamie 02.8.26 3339
2  가위 바위 보 게임 Jamie 02.8.26 5616
1  Two Input Logic Jamie 02.8.26 2582
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