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# 13 Jamie    02.8.29 13:25

1.Spec

up count를 설계해 봅시다. 입력 bit수는 12bit입니다.
시스템 clock인 clk의 상승에서 카운터의 출력 c_out[11:0]이 '1'씩 증가합니다.
만약 rst가 '1'이면 카운터의 출력은 '0'으로 초기화 되고, 그렇지 않은 경우
카운터를 합니다,
가장 기본적인 count이므로 쉽게 이해할 수 있을 겁니다.

2.Input/Output



3.Timing



4.Block Diagram



5.RTL Code : up_count.vhd
  Test Vector : up_count_tb.vhd
게시물: 93 건, 현재: 1 / 1 쪽
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85  [Verilog]Latch example JMJS 08.12.1 2363
84  Pad verilog example JMJS 01.3.16 4272
83  [ModelSim] vector JMJS 01.3.16 1965
82  RTL Code 분석순서 JMJS 09.4.29 2259
81  [temp]PIPE JMJS 08.10.2 1627
80  [temp]always-forever 무한루프 JMJS 08.10.2 1709
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74  [예]shift JMJS 02.6.19 1789
73  test JMJS 09.7.20 1570
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71  test JMJS 09.7.20 1313
70  test JMJS 09.7.20 1423
69  test JMJS 09.7.20 1450
68  test JMJS 09.7.20 1375
67  test JMJS 09.7.20 1296
66  test JMJS 09.7.20 1254
65  test JMJS 09.7.20 1362
64  test JMJS 09.7.20 1625
63  test JMJS 09.7.20 1610
62  test JMJS 09.7.20 1539
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56  test JMJS 09.7.20 1383
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51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4415
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49  Verdi JMJS 10.4.22 2805
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43  I2C Webpage JMJS 08.2.25 1540
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41  [Verilog]vstring JMJS 17.9.27 1776
40  Riviera Simple Case JMJS 09.4.29 2912
39  [VHDL]DES Example JMJS 07.6.15 2659
38  [verilog]RAM example JMJS 09.6.5 2436
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1696
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