LogIn E-mail
설계이야기
Mealy Machine
# 16 Jamie    02.8.29 13:33

1.Spec

이제 Mealy Machine에 대해 공부를 해보겠습니다.
앞에서 설명한 것처럼 Mealy Machine은 현상태와 입력값이 출력에 직접적인 영향을 미칩니다.
Moore machine과도 비교해서 공부해 보십시요.

2.Input/Output



3.Timing



4.Block Diagram



5.RTL Code : mealy_machine.vhd
  Test Vector : mealy_machine_tb.vhd

게시물: 93 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
95  draw_hexa.v JMJS 10.6.17 1752
94  jmjsxram3.v JMJS 10.4.9 1534
93  Verilog document JMJS 11.1.24 2088
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1705
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3069
90  gtkwave PC version JMJS 09.3.30 1531
89  ncsim option example JMJS 08.12.1 3714
88  [영상]keywords for web search JMJS 08.12.1 1501
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 5681
86  ncverilog option example JMJS 10.6.8 6799
85  [Verilog]Latch example JMJS 08.12.1 2108
84  Pad verilog example JMJS 01.3.16 3951
83  [ModelSim] vector JMJS 01.3.16 1707
82  RTL Code 분석순서 JMJS 09.4.29 1979
81  [temp]PIPE JMJS 08.10.2 1415
80  [temp]always-forever 무한루프 JMJS 08.10.2 1465
79  YCbCr2RGB.v JMJS 10.5.12 1655
78  [VHDL]rom64x8 JMJS 09.3.27 1288
77  [function]vector_compare JMJS 02.6.19 1237
76  [function]vector2integer JMJS 02.6.19 1336
75  [VHDL]ram8x4x8 JMJS 08.12.1 1210
74  [예]shift JMJS 02.6.19 1521
73  test JMJS 09.7.20 1306
72  test JMJS 09.7.20 1168
71  test JMJS 09.7.20 1079
70  test JMJS 09.7.20 1222
69  test JMJS 09.7.20 1233
68  test JMJS 09.7.20 1142
67  test JMJS 09.7.20 1067
66  test JMJS 09.7.20 1048
65  test JMJS 09.7.20 1144
64  test JMJS 09.7.20 1238
63  test JMJS 09.7.20 1233
62  test JMJS 09.7.20 1166
61  VHDL의 연산자 우선순위 JMJS 09.7.20 2793
60  test JMJS 09.7.20 1051
59  test JMJS 09.7.20 1146
58  test JMJS 09.7.20 1141
57  test JMJS 09.7.20 1101
56  test JMJS 09.7.20 1182
55  verilog 학과 샘플강의 JMJS 16.5.30 1427
54  [verilog]create_generated_clock JMJS 15.4.28 1531
53  [Verilog]JDIFF JMJS 14.7.4 1040
52  [verilog]parameter definition JMJS 14.3.5 1301
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 3796
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 1927
49  Verdi JMJS 10.4.22 2487
48  draw hexa JMJS 10.4.9 1308
47  asfifo - Async FIFO JMJS 10.4.8 1195
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 2742
45  synplify batch JMJS 10.3.8 1889
44  전자시계 Type A JMJS 08.11.28 1360
43  I2C Webpage JMJS 08.2.25 1321
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 4585
41  [Verilog]vstring JMJS 17.9.27 1563
40  Riviera Simple Case JMJS 09.4.29 2514
39  [VHDL]DES Example JMJS 07.6.15 2439
38  [verilog]RAM example JMJS 09.6.5 2173
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1498
36  Jamie's VHDL Handbook JMJS 08.11.28 2111
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2737
34  RTL Job JMJS 09.4.29 1563
33  [VHDL]type example - package TYPES JMJS 06.2.2 1268
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 8020
30  [verilog]array_module JMJS 05.12.8 1585
29  [verilog-2001]generate JMJS 05.12.8 2812
28  protected JMJS 05.11.18 1443
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2225
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1414
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 1868
23  Array Of Array JMJS 04.8.16 1497
22  dumpfile, dumpvars JMJS 04.7.19 2940
21  Vending Machine Jamie 02.12.16 9063
20  Mini Vending Machine1 Jamie 02.12.10 6029
19  Mini Vending Machine Jamie 02.12.6 8596
18  Key Jamie 02.11.29 4193
17  Stop Watch Jamie 02.11.25 4927
16  Mealy Machine Jamie 02.8.29 5655
15  Moore Machine Jamie 02.8.29 15313
14  Up Down Counter Jamie 02.8.29 3329
13  Up Counter Jamie 02.8.29 2219
12  Edge Detecter Jamie 02.8.29 2315
11  Concept4 Jamie 02.8.28 1546
10  Concept3 Jamie 02.8.28 1539
9  Concept2_1 Jamie 02.8.28 1433
8  Concept2 Jamie 02.8.28 1507
7  Concept1 Jamie 02.8.26 1709
6  Tri State Buffer Jamie 02.8.26 2954
5  8x3 Encoder Jamie 02.8.28 3335
4  3x8 Decoder Jamie 02.8.28 3116
3  4bit Comparator Jamie 02.8.26 2579
2  가위 바위 보 게임 Jamie 02.8.26 4513
1  Two Input Logic Jamie 02.8.26 1938
[1]