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test
# 62 JMJS    09.7.20 15:59

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 337
97  test plusargs value plusargs JMJS 24.9.5 351
96  color text JMJS 24.7.13 394
95  draw_hexa.v JMJS 10.6.17 2546
94  jmjsxram3.v JMJS 10.4.9 2470
93  Verilog document JMJS 11.1.24 3067
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2657
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4090
90  gtkwave PC version JMJS 09.3.30 2473
89  ncsim option example JMJS 08.12.1 4825
88  [영상]keywords for web search JMJS 08.12.1 2433
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6553
86  ncverilog option example JMJS 10.6.8 8287
85  [Verilog]Latch example JMJS 08.12.1 3024
84  Pad verilog example JMJS 01.3.16 4970
83  [ModelSim] vector JMJS 01.3.16 2657
82  RTL Code 분석순서 JMJS 09.4.29 2893
81  [temp]PIPE JMJS 08.10.2 2297
80  [temp]always-forever 무한루프 JMJS 08.10.2 2373
79  YCbCr2RGB.v JMJS 10.5.12 2561
78  [VHDL]rom64x8 JMJS 09.3.27 2111
77  [function]vector_compare JMJS 02.6.19 1997
76  [function]vector2integer JMJS 02.6.19 2223
75  [VHDL]ram8x4x8 JMJS 08.12.1 1937
74  [예]shift JMJS 02.6.19 2404
73  test JMJS 09.7.20 2264
72  test JMJS 09.7.20 1796
71  test JMJS 09.7.20 1975
70  test JMJS 09.7.20 2065
69  test JMJS 09.7.20 2115
68  test JMJS 09.7.20 2055
67  test JMJS 09.7.20 1987
66  test JMJS 09.7.20 1931
65  test JMJS 09.7.20 2058
64  test JMJS 09.7.20 2244
63  test JMJS 09.7.20 2287
62  test JMJS 09.7.20 2173
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3956
60  test JMJS 09.7.20 1726
59  test JMJS 09.7.20 2104
58  test JMJS 09.7.20 2009
57  test JMJS 09.7.20 1976
56  test JMJS 09.7.20 2009
55  verilog 학과 샘플강의 JMJS 16.5.30 2434
54  [verilog]create_generated_clock JMJS 15.4.28 2426
53  [Verilog]JDIFF JMJS 14.7.4 1852
52  [verilog]parameter definition JMJS 14.3.5 2123
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5065
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2699
49  Verdi JMJS 10.4.22 3613
48  draw hexa JMJS 10.4.9 2089
47  asfifo - Async FIFO JMJS 10.4.8 1952
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3636
45  synplify batch JMJS 10.3.8 2838
44  전자시계 Type A JMJS 08.11.28 2337
43  I2C Webpage JMJS 08.2.25 2164
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6250
41  [Verilog]vstring JMJS 17.9.27 2364
40  Riviera Simple Case JMJS 09.4.29 3450
39  [VHDL]DES Example JMJS 07.6.15 3331
38  [verilog]RAM example JMJS 09.6.5 3090
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2339
36  Jamie's VHDL Handbook JMJS 08.11.28 3036
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3613
34  RTL Job JMJS 09.4.29 2549
33  [VHDL]type example - package TYPES JMJS 06.2.2 1980
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9672
30  [verilog]array_module JMJS 05.12.8 2578
29  [verilog-2001]generate JMJS 05.12.8 3720
28  protected JMJS 05.11.18 2392
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3109
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2091
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2722
23  Array Of Array JMJS 04.8.16 2262
22  dumpfile, dumpvars JMJS 04.7.19 3968
21  Vending Machine Jamie 02.12.16 10398
20  Mini Vending Machine1 Jamie 02.12.10 7250
19  Mini Vending Machine Jamie 02.12.6 10087
18  Key Jamie 02.11.29 5301
17  Stop Watch Jamie 02.11.25 5824
16  Mealy Machine Jamie 02.8.29 7026
15  Moore Machine Jamie 02.8.29 18359
14  Up Down Counter Jamie 02.8.29 4389
13  Up Counter Jamie 02.8.29 3084
12  Edge Detecter Jamie 02.8.29 3299
11  Concept4 Jamie 02.8.28 2238
10  Concept3 Jamie 02.8.28 2357
9  Concept2_1 Jamie 02.8.28 2252
8  Concept2 Jamie 02.8.28 2342
7  Concept1 Jamie 02.8.26 2357
6  Tri State Buffer Jamie 02.8.26 3947
5  8x3 Encoder Jamie 02.8.28 4489
4  3x8 Decoder Jamie 02.8.28 4129
3  4bit Comparator Jamie 02.8.26 3500
2  가위 바위 보 게임 Jamie 02.8.26 5651
1  Two Input Logic Jamie 02.8.26 2761
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