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test
# 57 JMJS    09.7.20 16:00

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 253
97  test plusargs value plusargs JMJS 24.9.5 300
96  color text JMJS 24.7.13 306
95  draw_hexa.v JMJS 10.6.17 2507
94  jmjsxram3.v JMJS 10.4.9 2279
93  Verilog document JMJS 11.1.24 2893
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2477
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3891
90  gtkwave PC version JMJS 09.3.30 2246
89  ncsim option example JMJS 08.12.1 4619
88  [영상]keywords for web search JMJS 08.12.1 2251
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6494
86  ncverilog option example JMJS 10.6.8 8083
85  [Verilog]Latch example JMJS 08.12.1 2833
84  Pad verilog example JMJS 01.3.16 4746
83  [ModelSim] vector JMJS 01.3.16 2441
82  RTL Code 분석순서 JMJS 09.4.29 2725
81  [temp]PIPE JMJS 08.10.2 2097
80  [temp]always-forever 무한루프 JMJS 08.10.2 2189
79  YCbCr2RGB.v JMJS 10.5.12 2378
78  [VHDL]rom64x8 JMJS 09.3.27 1965
77  [function]vector_compare JMJS 02.6.19 1872
76  [function]vector2integer JMJS 02.6.19 2006
75  [VHDL]ram8x4x8 JMJS 08.12.1 1849
74  [예]shift JMJS 02.6.19 2259
73  test JMJS 09.7.20 2056
72  test JMJS 09.7.20 1758
71  test JMJS 09.7.20 1763
70  test JMJS 09.7.20 1858
69  test JMJS 09.7.20 1904
68  test JMJS 09.7.20 1848
67  test JMJS 09.7.20 1772
66  test JMJS 09.7.20 1748
65  test JMJS 09.7.20 1842
64  test JMJS 09.7.20 2051
63  test JMJS 09.7.20 2064
62  test JMJS 09.7.20 1985
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3795
60  test JMJS 09.7.20 1691
59  test JMJS 09.7.20 1856
58  test JMJS 09.7.20 1833
57  test JMJS 09.7.20 1788
56  test JMJS 09.7.20 1839
55  verilog 학과 샘플강의 JMJS 16.5.30 2383
54  [verilog]create_generated_clock JMJS 15.4.28 2355
53  [Verilog]JDIFF JMJS 14.7.4 1629
52  [verilog]parameter definition JMJS 14.3.5 1937
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4892
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2619
49  Verdi JMJS 10.4.22 3400
48  draw hexa JMJS 10.4.9 1983
47  asfifo - Async FIFO JMJS 10.4.8 1847
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3504
45  synplify batch JMJS 10.3.8 2618
44  전자시계 Type A JMJS 08.11.28 2140
43  I2C Webpage JMJS 08.2.25 1974
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6134
41  [Verilog]vstring JMJS 17.9.27 2207
40  Riviera Simple Case JMJS 09.4.29 3322
39  [VHDL]DES Example JMJS 07.6.15 3129
38  [verilog]RAM example JMJS 09.6.5 2890
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2167
36  Jamie's VHDL Handbook JMJS 08.11.28 2830
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3447
34  RTL Job JMJS 09.4.29 2297
33  [VHDL]type example - package TYPES JMJS 06.2.2 1907
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9499
30  [verilog]array_module JMJS 05.12.8 2416
29  [verilog-2001]generate JMJS 05.12.8 3525
28  protected JMJS 05.11.18 2184
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2984
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1961
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2610
23  Array Of Array JMJS 04.8.16 2127
22  dumpfile, dumpvars JMJS 04.7.19 3751
21  Vending Machine Jamie 02.12.16 10210
20  Mini Vending Machine1 Jamie 02.12.10 7092
19  Mini Vending Machine Jamie 02.12.6 9942
18  Key Jamie 02.11.29 5113
17  Stop Watch Jamie 02.11.25 5748
16  Mealy Machine Jamie 02.8.29 6857
15  Moore Machine Jamie 02.8.29 18167
14  Up Down Counter Jamie 02.8.29 4200
13  Up Counter Jamie 02.8.29 2885
12  Edge Detecter Jamie 02.8.29 3115
11  Concept4 Jamie 02.8.28 2171
10  Concept3 Jamie 02.8.28 2199
9  Concept2_1 Jamie 02.8.28 2088
8  Concept2 Jamie 02.8.28 2180
7  Concept1 Jamie 02.8.26 2326
6  Tri State Buffer Jamie 02.8.26 3689
5  8x3 Encoder Jamie 02.8.28 4303
4  3x8 Decoder Jamie 02.8.28 3962
3  4bit Comparator Jamie 02.8.26 3341
2  가위 바위 보 게임 Jamie 02.8.26 5617
1  Two Input Logic Jamie 02.8.26 2584
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