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test
# 57 JMJS    09.7.20 16:00

test
게시물: 96 건, 현재: 1 / 1 쪽
번호 제       목 작성자 등록일 방문
98  interface JMJS 25.1.20 296
97  test plusargs value plusargs JMJS 24.9.5 333
96  color text JMJS 24.7.13 351
95  draw_hexa.v JMJS 10.6.17 2527
94  jmjsxram3.v JMJS 10.4.9 2364
93  Verilog document JMJS 11.1.24 2976
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2544
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3973
90  gtkwave PC version JMJS 09.3.30 2340
89  ncsim option example JMJS 08.12.1 4714
88  [영상]keywords for web search JMJS 08.12.1 2318
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6528
86  ncverilog option example JMJS 10.6.8 8170
85  [Verilog]Latch example JMJS 08.12.1 2911
84  Pad verilog example JMJS 01.3.16 4848
83  [ModelSim] vector JMJS 01.3.16 2530
82  RTL Code 분석순서 JMJS 09.4.29 2799
81  [temp]PIPE JMJS 08.10.2 2184
80  [temp]always-forever 무한루프 JMJS 08.10.2 2270
79  YCbCr2RGB.v JMJS 10.5.12 2454
78  [VHDL]rom64x8 JMJS 09.3.27 2022
77  [function]vector_compare JMJS 02.6.19 1928
76  [function]vector2integer JMJS 02.6.19 2111
75  [VHDL]ram8x4x8 JMJS 08.12.1 1893
74  [예]shift JMJS 02.6.19 2319
73  test JMJS 09.7.20 2137
72  test JMJS 09.7.20 1777
71  test JMJS 09.7.20 1854
70  test JMJS 09.7.20 1953
69  test JMJS 09.7.20 1994
68  test JMJS 09.7.20 1929
67  test JMJS 09.7.20 1868
66  test JMJS 09.7.20 1819
65  test JMJS 09.7.20 1922
64  test JMJS 09.7.20 2131
63  test JMJS 09.7.20 2159
62  test JMJS 09.7.20 2074
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3860
60  test JMJS 09.7.20 1713
59  test JMJS 09.7.20 1958
58  test JMJS 09.7.20 1898
57  test JMJS 09.7.20 1868
56  test JMJS 09.7.20 1909
55  verilog 학과 샘플강의 JMJS 16.5.30 2418
54  [verilog]create_generated_clock JMJS 15.4.28 2387
53  [Verilog]JDIFF JMJS 14.7.4 1717
52  [verilog]parameter definition JMJS 14.3.5 2014
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4948
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2659
49  Verdi JMJS 10.4.22 3481
48  draw hexa JMJS 10.4.9 2027
47  asfifo - Async FIFO JMJS 10.4.8 1897
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3571
45  synplify batch JMJS 10.3.8 2711
44  전자시계 Type A JMJS 08.11.28 2223
43  I2C Webpage JMJS 08.2.25 2061
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 6211
41  [Verilog]vstring JMJS 17.9.27 2278
40  Riviera Simple Case JMJS 09.4.29 3366
39  [VHDL]DES Example JMJS 07.6.15 3207
38  [verilog]RAM example JMJS 09.6.5 2980
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2242
36  Jamie's VHDL Handbook JMJS 08.11.28 2900
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3507
34  RTL Job JMJS 09.4.29 2405
33  [VHDL]type example - package TYPES JMJS 06.2.2 1951
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9577
30  [verilog]array_module JMJS 05.12.8 2468
29  [verilog-2001]generate JMJS 05.12.8 3603
28  protected JMJS 05.11.18 2255
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 3031
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 2026
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2655
23  Array Of Array JMJS 04.8.16 2173
22  dumpfile, dumpvars JMJS 04.7.19 3841
21  Vending Machine Jamie 02.12.16 10283
20  Mini Vending Machine1 Jamie 02.12.10 7163
19  Mini Vending Machine Jamie 02.12.6 10011
18  Key Jamie 02.11.29 5181
17  Stop Watch Jamie 02.11.25 5790
16  Mealy Machine Jamie 02.8.29 6924
15  Moore Machine Jamie 02.8.29 18261
14  Up Down Counter Jamie 02.8.29 4275
13  Up Counter Jamie 02.8.29 2971
12  Edge Detecter Jamie 02.8.29 3194
11  Concept4 Jamie 02.8.28 2213
10  Concept3 Jamie 02.8.28 2263
9  Concept2_1 Jamie 02.8.28 2158
8  Concept2 Jamie 02.8.28 2244
7  Concept1 Jamie 02.8.26 2343
6  Tri State Buffer Jamie 02.8.26 3802
5  8x3 Encoder Jamie 02.8.28 4410
4  3x8 Decoder Jamie 02.8.28 4035
3  4bit Comparator Jamie 02.8.26 3412
2  가위 바위 보 게임 Jamie 02.8.26 5637
1  Two Input Logic Jamie 02.8.26 2653
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