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[Verilog]Latch example
#
85
JMJS
08.12.1 14:11
always @(a,b)
case(a)
2'd1: c<=b+1;
default: c<=c;
endcase
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interface
JMJS
25.1.20
329
97
test plusargs value plusargs
JMJS
24.9.5
348
96
color text
JMJS
24.7.13
388
95
draw_hexa.v
JMJS
10.6.17
2543
94
jmjsxram3.v
JMJS
10.4.9
2447
93
Verilog document
JMJS
11.1.24
3040
92
[verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3;
JMJS
09.3.31
2627
91
[verilog]forever, repeat, strobe, realtime, ...
JMJS
09.7.6
4067
90
gtkwave PC version
JMJS
09.3.30
2430
89
ncsim option example
JMJS
08.12.1
4796
88
[¿µ»ó]keywords for web search
JMJS
08.12.1
2397
87
[Verilog]fdisplay fopen fscanf
JMJS
11.1.24
6546
86
ncverilog option example
JMJS
10.6.8
8258
85
[Verilog]Latch example
JMJS
08.12.1
3000
84
Pad verilog example
JMJS
01.3.16
4937
83
[ModelSim] vector
JMJS
01.3.16
2623
82
RTL Code ºÐ¼®¼ø¼
JMJS
09.4.29
2869
81
[temp]PIPE
JMJS
08.10.2
2267
80
[temp]always-forever ¹«ÇÑ·çÇÁ
JMJS
08.10.2
2346
79
YCbCr2RGB.v
JMJS
10.5.12
2538
78
[VHDL]rom64x8
JMJS
09.3.27
2090
77
[function]vector_compare
JMJS
02.6.19
1986
76
[function]vector2integer
JMJS
02.6.19
2192
75
[VHDL]ram8x4x8
JMJS
08.12.1
1924
74
[¿¹]shift
JMJS
02.6.19
2383
73
test
JMJS
09.7.20
2230
72
test
JMJS
09.7.20
1791
71
test
JMJS
09.7.20
1947
70
test
JMJS
09.7.20
2035
69
test
JMJS
09.7.20
2081
68
test
JMJS
09.7.20
2019
67
test
JMJS
09.7.20
1954
66
test
JMJS
09.7.20
1901
65
test
JMJS
09.7.20
2021
64
test
JMJS
09.7.20
2215
63
test
JMJS
09.7.20
2251
62
test
JMJS
09.7.20
2142
61
VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§
JMJS
09.7.20
3933
60
test
JMJS
09.7.20
1723
59
test
JMJS
09.7.20
2069
58
test
JMJS
09.7.20
1980
57
test
JMJS
09.7.20
1948
56
test
JMJS
09.7.20
1985
55
verilog Çаú »ùÇðÀÇ
JMJS
16.5.30
2430
54
[verilog]create_generated_clock
JMJS
15.4.28
2415
53
[Verilog]JDIFF
JMJS
14.7.4
1815
52
[verilog]parameter definition
JMJS
14.3.5
2094
51
[verilog]sformat fopen fscanf fwrite fclose
JMJS
12.1.31
5032
50
Verilog File I/0,Verilog file handling
JMJS
12.1.30
2688
49
Verdi
JMJS
10.4.22
3578
48
draw hexa
JMJS
10.4.9
2079
47
asfifo - Async FIFO
JMJS
10.4.8
1938
46
VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡
JMJS
02.3.14
3619
45
synplify batch
JMJS
10.3.8
2813
44
ÀüÀڽðè Type A
JMJS
08.11.28
2305
43
I2C Webpage
JMJS
08.2.25
2139
42
PC¿¡¼ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog)
JMJS
13.1.14
6243
41
[Verilog]vstring
JMJS
17.9.27
2345
40
Riviera Simple Case
JMJS
09.4.29
3436
39
[VHDL]DES Example
JMJS
07.6.15
3295
38
[verilog]RAM example
JMJS
09.6.5
3072
37
ROM example [VerilogHDL, RTL]
JMJS
04.5.27
2310
36
Jamie's VHDL Handbook
JMJS
08.11.28
3000
35
Dualport RAM example [VerilogHDL, RTL]
JMJS
04.5.27
3580
34
RTL Job
JMJS
09.4.29
2517
33
[VHDL]type example - package TYPES
JMJS
06.2.2
1972
32
[verilog]`define `ifdef `elsif `else `endif ...
JMJS
10.5.11
9646
30
[verilog]array_module
JMJS
05.12.8
2549
29
[verilog-2001]generate
JMJS
05.12.8
3695
28
protected
JMJS
05.11.18
2351
27
design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä?
JMJS
09.7.20
3087
26
busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº?
JMJS
04.11.9
2079
25
component¸¦ »ý¼ºÇؼ ´Ù¸¥ °÷¿¡¼ È£ÃâÇÏ´Â ¹æ¹ý
JMJS
04.11.4
2710
23
Array Of Array
JMJS
04.8.16
2238
22
dumpfile, dumpvars
JMJS
04.7.19
3932
21
Vending Machine
Jamie
02.12.16
10371
20
Mini Vending Machine1
Jamie
02.12.10
7236
19
Mini Vending Machine
Jamie
02.12.6
10071
18
Key
Jamie
02.11.29
5275
17
Stop Watch
Jamie
02.11.25
5814
16
Mealy Machine
Jamie
02.8.29
6989
15
Moore Machine
Jamie
02.8.29
18337
14
Up Down Counter
Jamie
02.8.29
4358
13
Up Counter
Jamie
02.8.29
3048
12
Edge Detecter
Jamie
02.8.29
3266
11
Concept4
Jamie
02.8.28
2233
10
Concept3
Jamie
02.8.28
2333
9
Concept2_1
Jamie
02.8.28
2225
8
Concept2
Jamie
02.8.28
2313
7
Concept1
Jamie
02.8.26
2355
6
Tri State Buffer
Jamie
02.8.26
3914
5
8x3 Encoder
Jamie
02.8.28
4460
4
3x8 Decoder
Jamie
02.8.28
4101
3
4bit Comparator
Jamie
02.8.26
3476
2
°¡À§ ¹ÙÀ§ º¸ °ÔÀÓ
Jamie
02.8.26
5648
1
Two Input Logic
Jamie
02.8.26
2731
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