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[Verilog]Latch example
#
85
JMJS
08.12.1 14:11
always @(a,b)
case(a)
2'd1: c<=b+1;
default: c<=c;
endcase
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interface
JMJS
25.1.20
352
97
test plusargs value plusargs
JMJS
24.9.5
358
96
color text
JMJS
24.7.13
412
95
draw_hexa.v
JMJS
10.6.17
2562
94
jmjsxram3.v
JMJS
10.4.9
2535
93
Verilog document
JMJS
11.1.24
3106
92
[verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3;
JMJS
09.3.31
2716
91
[verilog]forever, repeat, strobe, realtime, ...
JMJS
09.7.6
4144
90
gtkwave PC version
JMJS
09.3.30
2530
89
ncsim option example
JMJS
08.12.1
4880
88
[¿µ»ó]keywords for web search
JMJS
08.12.1
2481
87
[Verilog]fdisplay fopen fscanf
JMJS
11.1.24
6571
86
ncverilog option example
JMJS
10.6.8
8350
85
[Verilog]Latch example
JMJS
08.12.1
3074
84
Pad verilog example
JMJS
01.3.16
5027
83
[ModelSim] vector
JMJS
01.3.16
2703
82
RTL Code ºÐ¼®¼ø¼
JMJS
09.4.29
2952
81
[temp]PIPE
JMJS
08.10.2
2361
80
[temp]always-forever ¹«ÇÑ·çÇÁ
JMJS
08.10.2
2446
79
YCbCr2RGB.v
JMJS
10.5.12
2593
78
[VHDL]rom64x8
JMJS
09.3.27
2158
77
[function]vector_compare
JMJS
02.6.19
2016
76
[function]vector2integer
JMJS
02.6.19
2282
75
[VHDL]ram8x4x8
JMJS
08.12.1
1973
74
[¿¹]shift
JMJS
02.6.19
2449
73
test
JMJS
09.7.20
2320
72
test
JMJS
09.7.20
1807
71
test
JMJS
09.7.20
2050
70
test
JMJS
09.7.20
2124
69
test
JMJS
09.7.20
2169
68
test
JMJS
09.7.20
2115
67
test
JMJS
09.7.20
2053
66
test
JMJS
09.7.20
2008
65
test
JMJS
09.7.20
2124
64
test
JMJS
09.7.20
2290
63
test
JMJS
09.7.20
2347
62
test
JMJS
09.7.20
2234
61
VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§
JMJS
09.7.20
4022
60
test
JMJS
09.7.20
1739
59
test
JMJS
09.7.20
2167
58
test
JMJS
09.7.20
2082
57
test
JMJS
09.7.20
2030
56
test
JMJS
09.7.20
2085
55
verilog Çаú »ùÇðÀÇ
JMJS
16.5.30
2447
54
[verilog]create_generated_clock
JMJS
15.4.28
2445
53
[Verilog]JDIFF
JMJS
14.7.4
1909
52
[verilog]parameter definition
JMJS
14.3.5
2186
51
[verilog]sformat fopen fscanf fwrite fclose
JMJS
12.1.31
5136
50
Verilog File I/0,Verilog file handling
JMJS
12.1.30
2713
49
Verdi
JMJS
10.4.22
3652
48
draw hexa
JMJS
10.4.9
2106
47
asfifo - Async FIFO
JMJS
10.4.8
1974
46
VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡
JMJS
02.3.14
3674
45
synplify batch
JMJS
10.3.8
2879
44
ÀüÀڽðè Type A
JMJS
08.11.28
2408
43
I2C Webpage
JMJS
08.2.25
2229
42
PC¿¡¼ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog)
JMJS
13.1.14
6260
41
[Verilog]vstring
JMJS
17.9.27
2395
40
Riviera Simple Case
JMJS
09.4.29
3491
39
[VHDL]DES Example
JMJS
07.6.15
3395
38
[verilog]RAM example
JMJS
09.6.5
3173
37
ROM example [VerilogHDL, RTL]
JMJS
04.5.27
2401
36
Jamie's VHDL Handbook
JMJS
08.11.28
3073
35
Dualport RAM example [VerilogHDL, RTL]
JMJS
04.5.27
3677
34
RTL Job
JMJS
09.4.29
2604
33
[VHDL]type example - package TYPES
JMJS
06.2.2
2001
32
[verilog]`define `ifdef `elsif `else `endif ...
JMJS
10.5.11
9717
30
[verilog]array_module
JMJS
05.12.8
2622
29
[verilog-2001]generate
JMJS
05.12.8
3773
28
protected
JMJS
05.11.18
2461
27
design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä?
JMJS
09.7.20
3147
26
busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº?
JMJS
04.11.9
2109
25
component¸¦ »ý¼ºÇؼ ´Ù¸¥ °÷¿¡¼ È£ÃâÇÏ´Â ¹æ¹ý
JMJS
04.11.4
2764
23
Array Of Array
JMJS
04.8.16
2308
22
dumpfile, dumpvars
JMJS
04.7.19
4017
21
Vending Machine
Jamie
02.12.16
10446
20
Mini Vending Machine1
Jamie
02.12.10
7324
19
Mini Vending Machine
Jamie
02.12.6
10123
18
Key
Jamie
02.11.29
5349
17
Stop Watch
Jamie
02.11.25
5841
16
Mealy Machine
Jamie
02.8.29
7065
15
Moore Machine
Jamie
02.8.29
18410
14
Up Down Counter
Jamie
02.8.29
4468
13
Up Counter
Jamie
02.8.29
3155
12
Edge Detecter
Jamie
02.8.29
3348
11
Concept4
Jamie
02.8.28
2253
10
Concept3
Jamie
02.8.28
2410
9
Concept2_1
Jamie
02.8.28
2289
8
Concept2
Jamie
02.8.28
2368
7
Concept1
Jamie
02.8.26
2368
6
Tri State Buffer
Jamie
02.8.26
4002
5
8x3 Encoder
Jamie
02.8.28
4562
4
3x8 Decoder
Jamie
02.8.28
4185
3
4bit Comparator
Jamie
02.8.26
3568
2
°¡À§ ¹ÙÀ§ º¸ °ÔÀÓ
Jamie
02.8.26
5662
1
Two Input Logic
Jamie
02.8.26
2820
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