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dumpfile, dumpvars
# 22 JMJS    04.7.19 21:12

// create waveform file
initial begin
   $display("start simulation");
   $dumpfile("wave.vcd");
   $dumpvars(0,displayCoin);
   $dumpvars(0,outputWater);
   $dumpvars(0,f);
   #10000 $finish;
end

initial begin
   $monitor ( $time, " ", CLK, pllclk, onepulseclk );
   $dumpfile ( "tb.vcd" );
   $dumpvars ( 1, CLK, pllclk, onepulseclk );
   CLK = 0;
   #2000;
   $finish;
end

initial begin
   $monitor ( $time, " ", CLK );
   $dumpfile ( "pll.vcd" );
   $dumpvars;
   CLK = 0;
end

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62  test JMJS 09.7.20 2159
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41  [Verilog]vstring JMJS 17.9.27 2360
40  Riviera Simple Case JMJS 09.4.29 3441
39  [VHDL]DES Example JMJS 07.6.15 3315
38  [verilog]RAM example JMJS 09.6.5 3078
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2326
36  Jamie's VHDL Handbook JMJS 08.11.28 3020
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34  RTL Job JMJS 09.4.29 2533
33  [VHDL]type example - package TYPES JMJS 06.2.2 1975
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