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Mini Vending Machine1
# 20 Jamie    02.12.10 12:07

1.Spec

   Mini vending machine1Àº mini vending machine°ú functionÀº µ¿ÀÏÇϳª
architecture¹®À» º¯ÇüÇÏ¿´½À´Ï´Ù.
   Ãâ·Â¿¡ ´ëÇØ °¢°¢ÀÇ process¹®À» »ç¿ëÇÏ¿© ȸ·Î¸¦ Á» ´õ »¡¸® ÀÌÇØÇϵµ·Ï ÇÏ¿´½À´Ï´Ù.
   µðÀÚÀο¡ µû¶ó Descriptin¹æ½ÄÀÌ ¾î´À °ÍÀÌ º¸´Ù È¿¿ïÀûÀÎÁö °áÁ¤µÇ°ÚÁö¸¸
ÇϳªÀÇ Ãâ·Â¿¡ ÇϳªÀÇ process¹®À» ÇÒ´çÇÏ´Â °ÍÀ» ¿ì¼±ÇÕ´Ï´Ù.

2.Input/Output



3.Timing



4.Block Diagram



5.VHDL Code : mini_vending_machine1.vhd
  Test Vector : mini_vending_machine1_tb.vhd

°Ô½Ã¹°: 96 °Ç, ÇöÀç: 1 / 1 ÂÊ
¹øÈ£ Á¦       ¸ñ ÀÛ¼ºÀÚ µî·ÏÀÏ ¹æ¹®
98  interface JMJS 25.1.20 296
97  test plusargs value plusargs JMJS 24.9.5 333
96  color text JMJS 24.7.13 350
95  draw_hexa.v JMJS 10.6.17 2527
94  jmjsxram3.v JMJS 10.4.9 2361
93  Verilog document JMJS 11.1.24 2975
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2543
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3969
90  gtkwave PC version JMJS 09.3.30 2339
89  ncsim option example JMJS 08.12.1 4713
88  [¿µ»ó]keywords for web search JMJS 08.12.1 2317
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6526
86  ncverilog option example JMJS 10.6.8 8169
85  [Verilog]Latch example JMJS 08.12.1 2910
84  Pad verilog example JMJS 01.3.16 4846
83  [ModelSim] vector JMJS 01.3.16 2527
82  RTL Code ºÐ¼®¼ø¼­ JMJS 09.4.29 2798
81  [temp]PIPE JMJS 08.10.2 2181
80  [temp]always-forever ¹«ÇÑ·çÇÁ JMJS 08.10.2 2269
79  YCbCr2RGB.v JMJS 10.5.12 2453
78  [VHDL]rom64x8 JMJS 09.3.27 2020
77  [function]vector_compare JMJS 02.6.19 1926
76  [function]vector2integer JMJS 02.6.19 2110
75  [VHDL]ram8x4x8 JMJS 08.12.1 1892
74  [¿¹]shift JMJS 02.6.19 2317
73  test JMJS 09.7.20 2134
72  test JMJS 09.7.20 1777
71  test JMJS 09.7.20 1852
70  test JMJS 09.7.20 1951
69  test JMJS 09.7.20 1991
68  test JMJS 09.7.20 1927
67  test JMJS 09.7.20 1864
66  test JMJS 09.7.20 1818
65  test JMJS 09.7.20 1920
64  test JMJS 09.7.20 2130
63  test JMJS 09.7.20 2158
62  test JMJS 09.7.20 2072
61  VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§ JMJS 09.7.20 3859
60  test JMJS 09.7.20 1713
59  test JMJS 09.7.20 1956
58  test JMJS 09.7.20 1897
57  test JMJS 09.7.20 1865
56  test JMJS 09.7.20 1907
55  verilog Çаú »ùÇð­ÀÇ JMJS 16.5.30 2417
54  [verilog]create_generated_clock JMJS 15.4.28 2387
53  [Verilog]JDIFF JMJS 14.7.4 1715
52  [verilog]parameter definition JMJS 14.3.5 2014
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4947
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2658
49  Verdi JMJS 10.4.22 3479
48  draw hexa JMJS 10.4.9 2025
47  asfifo - Async FIFO JMJS 10.4.8 1897
46  VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡ JMJS 02.3.14 3569
45  synplify batch JMJS 10.3.8 2709
44  ÀüÀڽðè Type A JMJS 08.11.28 2221
43  I2C Webpage JMJS 08.2.25 2059
42  PC¿¡¼­ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog) JMJS 13.1.14 6210
41  [Verilog]vstring JMJS 17.9.27 2275
40  Riviera Simple Case JMJS 09.4.29 3364
39  [VHDL]DES Example JMJS 07.6.15 3204
38  [verilog]RAM example JMJS 09.6.5 2979
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2242
36  Jamie's VHDL Handbook JMJS 08.11.28 2899
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3505
34  RTL Job JMJS 09.4.29 2403
33  [VHDL]type example - package TYPES JMJS 06.2.2 1949
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9575
30  [verilog]array_module JMJS 05.12.8 2467
29  [verilog-2001]generate JMJS 05.12.8 3601
28  protected JMJS 05.11.18 2254
27  design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä? JMJS 09.7.20 3030
26  busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº? JMJS 04.11.9 2023
25  component¸¦ »ý¼ºÇؼ­ ´Ù¸¥ °÷¿¡¼­ È£ÃâÇÏ´Â ¹æ¹ý JMJS 04.11.4 2654
23  Array Of Array JMJS 04.8.16 2172
22  dumpfile, dumpvars JMJS 04.7.19 3838
21  Vending Machine Jamie 02.12.16 10281
20  Mini Vending Machine1 Jamie 02.12.10 7162
19  Mini Vending Machine Jamie 02.12.6 10011
18  Key Jamie 02.11.29 5178
17  Stop Watch Jamie 02.11.25 5790
16  Mealy Machine Jamie 02.8.29 6922
15  Moore Machine Jamie 02.8.29 18259
14  Up Down Counter Jamie 02.8.29 4274
13  Up Counter Jamie 02.8.29 2971
12  Edge Detecter Jamie 02.8.29 3193
11  Concept4 Jamie 02.8.28 2212
10  Concept3 Jamie 02.8.28 2262
9  Concept2_1 Jamie 02.8.28 2157
8  Concept2 Jamie 02.8.28 2244
7  Concept1 Jamie 02.8.26 2343
6  Tri State Buffer Jamie 02.8.26 3801
5  8x3 Encoder Jamie 02.8.28 4407
4  3x8 Decoder Jamie 02.8.28 4033
3  4bit Comparator Jamie 02.8.26 3411
2  °¡À§ ¹ÙÀ§ º¸ °ÔÀÓ Jamie 02.8.26 5637
1  Two Input Logic Jamie 02.8.26 2652
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