LogIn E-mail
¼³°èÀ̾߱â
Key
# 18 Jamie    02.11.29 17:38

1.Spec

À̹ø¿¡´Â ÀüÀÚ۸¦ ¼³°èÇϰíÀÚ ÇÕ´Ï´Ù.
ÀÌ ÀüÀÚŰ´Â 8°³ÀÇ keypad¸¦ °¡Áö°í ÀÖ°í, Ãâ·ÂÀ¸·Î beep°ú door°¡ ÀÖ½À´Ï´Ù.
ÀüÀÚŰÀÇ ¹®À» ¿­·Á¸é 3->7->2->5¹ø ¼øÀ¸·Î keypad ÀÔ·ÂÀ» ¹Þ¾Æ¾ß ÇÕ´Ï´Ù.
ÀÌ ¼ø¼­·Î ÀԷµǸé door='1'ÀÌµÇ¾î ¹®ÀÌ ¿­¸®°í,  ÀԷ¼ø¼­°¡ ÀÌ¿Í ´Ù¸£¸é door='0'À» À¯ÁöÇϰí,
beep='1'ÀÌ µÇ¾î °æ°íÀ½ÀÌ ¿ï¸°´Ù°í °¡Á¤ÇÕ´Ï´Ù.
ÀԷ´ë±â »óÅÂÀÎ state0¿¡¼­ state1->state2->state3->state4·Î °¡¸ç,
state4¿¡¼­ door='1'ÀÌ µË´Ï´Ù.
±×·¯³ª ÀԷ¼ø¼­°¡ ¸ÂÁö ¾ÊÀ»°æ¿ì error»óÅ·Π°¡´Âµ¥ ÀÌ ¶§¿¡µµ 4°³ÀÇ keypad ÀÔ·ÂÀÌ ÀÖ¾î¾ß¸¸
beep='1'ÀÌ µÇ°Ô ÇÏ¿´½À´Ï´Ù.
ÀÌ ¶§ À¯È¿ÇÑ keyÀÔ·ÂÀ» ¹Þ¾ÆµéÀ̱â À§ÇØ key_en, key_en1 signalÀ» ÀÌ¿ëÇÏ¿©
keyÀÔ·Â »ó½Â¿©ºÎ¸¦ checkÇϵµ·Ï ¼³°èÇÏ¿´½À´Ï´Ù.

2,Input/Output



3.Timing



4.Block Diagram



5.VHDL Code : key.vhd
  Test Vector : key_tb.vhd

°Ô½Ã¹°: 96 °Ç, ÇöÀç: 1 / 1 ÂÊ
¹øÈ£ Á¦       ¸ñ ÀÛ¼ºÀÚ µî·ÏÀÏ ¹æ¹®
98  interface JMJS 25.1.20 336
97  test plusargs value plusargs JMJS 24.9.5 350
96  color text JMJS 24.7.13 392
95  draw_hexa.v JMJS 10.6.17 2545
94  jmjsxram3.v JMJS 10.4.9 2464
93  Verilog document JMJS 11.1.24 3063
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2653
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4085
90  gtkwave PC version JMJS 09.3.30 2466
89  ncsim option example JMJS 08.12.1 4820
88  [¿µ»ó]keywords for web search JMJS 08.12.1 2427
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6551
86  ncverilog option example JMJS 10.6.8 8284
85  [Verilog]Latch example JMJS 08.12.1 3020
84  Pad verilog example JMJS 01.3.16 4965
83  [ModelSim] vector JMJS 01.3.16 2650
82  RTL Code ºÐ¼®¼ø¼­ JMJS 09.4.29 2887
81  [temp]PIPE JMJS 08.10.2 2293
80  [temp]always-forever ¹«ÇÑ·çÇÁ JMJS 08.10.2 2369
79  YCbCr2RGB.v JMJS 10.5.12 2557
78  [VHDL]rom64x8 JMJS 09.3.27 2107
77  [function]vector_compare JMJS 02.6.19 1995
76  [function]vector2integer JMJS 02.6.19 2219
75  [VHDL]ram8x4x8 JMJS 08.12.1 1933
74  [¿¹]shift JMJS 02.6.19 2400
73  test JMJS 09.7.20 2259
72  test JMJS 09.7.20 1795
71  test JMJS 09.7.20 1971
70  test JMJS 09.7.20 2061
69  test JMJS 09.7.20 2109
68  test JMJS 09.7.20 2051
67  test JMJS 09.7.20 1980
66  test JMJS 09.7.20 1924
65  test JMJS 09.7.20 2051
64  test JMJS 09.7.20 2241
63  test JMJS 09.7.20 2283
62  test JMJS 09.7.20 2168
61  VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§ JMJS 09.7.20 3955
60  test JMJS 09.7.20 1725
59  test JMJS 09.7.20 2101
58  test JMJS 09.7.20 2004
57  test JMJS 09.7.20 1974
56  test JMJS 09.7.20 2006
55  verilog Çаú »ùÇð­ÀÇ JMJS 16.5.30 2433
54  [verilog]create_generated_clock JMJS 15.4.28 2424
53  [Verilog]JDIFF JMJS 14.7.4 1847
52  [verilog]parameter definition JMJS 14.3.5 2119
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5059
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2697
49  Verdi JMJS 10.4.22 3608
48  draw hexa JMJS 10.4.9 2087
47  asfifo - Async FIFO JMJS 10.4.8 1950
46  VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡ JMJS 02.3.14 3631
45  synplify batch JMJS 10.3.8 2833
44  ÀüÀڽðè Type A JMJS 08.11.28 2334
43  I2C Webpage JMJS 08.2.25 2159
42  PC¿¡¼­ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog) JMJS 13.1.14 6248
41  [Verilog]vstring JMJS 17.9.27 2361
40  Riviera Simple Case JMJS 09.4.29 3446
39  [VHDL]DES Example JMJS 07.6.15 3327
38  [verilog]RAM example JMJS 09.6.5 3085
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2335
36  Jamie's VHDL Handbook JMJS 08.11.28 3031
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3610
34  RTL Job JMJS 09.4.29 2544
33  [VHDL]type example - package TYPES JMJS 06.2.2 1978
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9666
30  [verilog]array_module JMJS 05.12.8 2574
29  [verilog-2001]generate JMJS 05.12.8 3717
28  protected JMJS 05.11.18 2386
27  design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä? JMJS 09.7.20 3103
26  busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº? JMJS 04.11.9 2090
25  component¸¦ »ý¼ºÇؼ­ ´Ù¸¥ °÷¿¡¼­ È£ÃâÇÏ´Â ¹æ¹ý JMJS 04.11.4 2721
23  Array Of Array JMJS 04.8.16 2258
22  dumpfile, dumpvars JMJS 04.7.19 3965
21  Vending Machine Jamie 02.12.16 10396
20  Mini Vending Machine1 Jamie 02.12.10 7247
19  Mini Vending Machine Jamie 02.12.6 10083
18  Key Jamie 02.11.29 5298
17  Stop Watch Jamie 02.11.25 5822
16  Mealy Machine Jamie 02.8.29 7022
15  Moore Machine Jamie 02.8.29 18355
14  Up Down Counter Jamie 02.8.29 4384
13  Up Counter Jamie 02.8.29 3077
12  Edge Detecter Jamie 02.8.29 3294
11  Concept4 Jamie 02.8.28 2236
10  Concept3 Jamie 02.8.28 2353
9  Concept2_1 Jamie 02.8.28 2249
8  Concept2 Jamie 02.8.28 2338
7  Concept1 Jamie 02.8.26 2356
6  Tri State Buffer Jamie 02.8.26 3942
5  8x3 Encoder Jamie 02.8.28 4485
4  3x8 Decoder Jamie 02.8.28 4124
3  4bit Comparator Jamie 02.8.26 3496
2  °¡À§ ¹ÙÀ§ º¸ °ÔÀÓ Jamie 02.8.26 5650
1  Two Input Logic Jamie 02.8.26 2756
[1]