4bitÀÇ ÀÔ·ÂÀ» °¢°¢ÀÇ bit·Î ³ª´©¾î Ãâ·ÂÇÏ°í ½ÍÀ»¶§´Â ¾î¶»°Ô ÇÏ¸é µÉ±î¿ä? ¾ÆÁÖ °£´ÜÇÕ´Ï´Ù. ¾Æ·¡ÀÇ Äڵ带 ÂüÁ¶Çϼ¼¿ä. library ieee; use ieee.std_logic_1164.all; entity bus2bit is port(I : in std_logic_vector(3 downto 0); o_3, o_2, o_1, o_0 : out std_logic); end bus2bit; architecture JMJS_Logic of bus2bit is begin o_3 <= I(3); o_2 <= I(2); o_1 <= I(1); o_0 <= I(0); end JMJS_Logic;