LogIn E-mail
¼³°èÀ̾߱â
[Verilog]vstring
# 41 JMJS    17.9.27 15:36

Strings in Verilog
A quick reference on a couple of ways to manipulate strings in Verilog HDL.
Declaration
There is no string data type is Verilog, so use the following to declare a register to hold a string.

reg[n*8:0] string;

Where the maximum length of the string is n characters. It takes 8 bits to store each character.
Usage
string = "Hello World"; $sdisplay("%s", string); // will get "Hello World"

Also, normal concatination will work, for the most part. So something like:

string = {"/path/to/file","/","filename",".txt"};

will result in a string useful to pass to $open to open a file.

For anything more advanced, a very good function is

$sformat(string,"%s %d %s",str1,num,str2);

would produce the string with the three varibles concatinated together and spaces in between.

//------------------------------------------------------------------------------------------------------------------------------------------

module vstring ();

function [10 *8 -1:0] int2str;
input [31:0] inum;
begin
        int2str = 0;
        while(inum > 0) begin
                int2str = {"0" + (inum - (inum/10)*10), int2str[79:8]};
                inum = inum / 10;
        end
end
endfunction

function [256 *8 -1:0] strfilter;
input [256 *8 -1:0] iline;
input [7:0] cnum;
integer i;
begin
        strfilter = 0;
        for(i=0;(i<256)&&(cnum>0); i=i+1) begin
                if(iline[2047:2040] != 0) begin
                        strfilter = {strfilter, iline[2047:2040]};
                        cnum = cnum -1;
                end
                iline = iline<<8;
        end
        while(cnum>0) begin
                strfilter = {strfilter, 8'h0};
                cnum = cnum -1;
        end
end
endfunction

`define ULINE "./cpu/u"
reg [32 *8 -1:0] num32;
reg [ 2 *8 -1:0] num2;
integer fp;
integer i;
initial begin
        for(i=8;i<12;i=i+1) begin
                num2 = "0" +i -(i/10)*10;
                if(i/10) num2[15:8] = "0" + i/10;
                num32 = strfilter({`ULINE, num2, "_A_",int2str(i),".txt"},32);
                $display("%s",num32);
                fp = $fopen(num32);
                $fwrite(fp,"%s",num32);
                $fclose(fp);
        end
end
endmodule

°Ô½Ã¹°: 96 °Ç, ÇöÀç: 1 / 1 ÂÊ
¹øÈ£ Á¦       ¸ñ ÀÛ¼ºÀÚ µî·ÏÀÏ ¹æ¹®
98  interface JMJS 25.1.20 167
97  test plusargs value plusargs JMJS 24.9.5 235
96  color text JMJS 24.7.13 240
95  draw_hexa.v JMJS 10.6.17 2440
94  jmjsxram3.v JMJS 10.4.9 2168
93  Verilog document JMJS 11.1.24 2770
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2349
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3779
90  gtkwave PC version JMJS 09.3.30 2104
89  ncsim option example JMJS 08.12.1 4497
88  [¿µ»ó]keywords for web search JMJS 08.12.1 2130
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6444
86  ncverilog option example JMJS 10.6.8 7946
85  [Verilog]Latch example JMJS 08.12.1 2716
84  Pad verilog example JMJS 01.3.16 4642
83  [ModelSim] vector JMJS 01.3.16 2329
82  RTL Code ºÐ¼®¼ø¼­ JMJS 09.4.29 2616
81  [temp]PIPE JMJS 08.10.2 1977
80  [temp]always-forever ¹«ÇÑ·çÇÁ JMJS 08.10.2 2055
79  YCbCr2RGB.v JMJS 10.5.12 2283
78  [VHDL]rom64x8 JMJS 09.3.27 1871
77  [function]vector_compare JMJS 02.6.19 1823
76  [function]vector2integer JMJS 02.6.19 1903
75  [VHDL]ram8x4x8 JMJS 08.12.1 1785
74  [¿¹]shift JMJS 02.6.19 2143
73  test JMJS 09.7.20 1929
72  test JMJS 09.7.20 1715
71  test JMJS 09.7.20 1647
70  test JMJS 09.7.20 1742
69  test JMJS 09.7.20 1790
68  test JMJS 09.7.20 1720
67  test JMJS 09.7.20 1636
66  test JMJS 09.7.20 1613
65  test JMJS 09.7.20 1713
64  test JMJS 09.7.20 1941
63  test JMJS 09.7.20 1955
62  test JMJS 09.7.20 1866
61  VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§ JMJS 09.7.20 3671
60  test JMJS 09.7.20 1649
59  test JMJS 09.7.20 1740
58  test JMJS 09.7.20 1712
57  test JMJS 09.7.20 1664
56  test JMJS 09.7.20 1705
55  verilog Çаú »ùÇð­ÀÇ JMJS 16.5.30 2317
54  [verilog]create_generated_clock JMJS 15.4.28 2309
53  [Verilog]JDIFF JMJS 14.7.4 1574
52  [verilog]parameter definition JMJS 14.3.5 1838
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4796
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2572
49  Verdi JMJS 10.4.22 3278
48  draw hexa JMJS 10.4.9 1924
47  asfifo - Async FIFO JMJS 10.4.8 1766
46  VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡ JMJS 02.3.14 3396
45  synplify batch JMJS 10.3.8 2499
44  ÀüÀڽðè Type A JMJS 08.11.28 2012
43  I2C Webpage JMJS 08.2.25 1861
42  PC¿¡¼­ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog) JMJS 13.1.14 6021
41  [Verilog]vstring JMJS 17.9.27 2106
40  Riviera Simple Case JMJS 09.4.29 3236
39  [VHDL]DES Example JMJS 07.6.15 2993
38  [verilog]RAM example JMJS 09.6.5 2759
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2035
36  Jamie's VHDL Handbook JMJS 08.11.28 2706
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3339
34  RTL Job JMJS 09.4.29 2178
33  [VHDL]type example - package TYPES JMJS 06.2.2 1847
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9382
30  [verilog]array_module JMJS 05.12.8 2319
29  [verilog-2001]generate JMJS 05.12.8 3406
28  protected JMJS 05.11.18 2076
27  design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä? JMJS 09.7.20 2886
26  busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº? JMJS 04.11.9 1917
25  component¸¦ »ý¼ºÇؼ­ ´Ù¸¥ °÷¿¡¼­ È£ÃâÇÏ´Â ¹æ¹ý JMJS 04.11.4 2507
23  Array Of Array JMJS 04.8.16 2021
22  dumpfile, dumpvars JMJS 04.7.19 3626
21  Vending Machine Jamie 02.12.16 10100
20  Mini Vending Machine1 Jamie 02.12.10 6981
19  Mini Vending Machine Jamie 02.12.6 9834
18  Key Jamie 02.11.29 5002
17  Stop Watch Jamie 02.11.25 5698
16  Mealy Machine Jamie 02.8.29 6756
15  Moore Machine Jamie 02.8.29 17984
14  Up Down Counter Jamie 02.8.29 4091
13  Up Counter Jamie 02.8.29 2790
12  Edge Detecter Jamie 02.8.29 2994
11  Concept4 Jamie 02.8.28 2129
10  Concept3 Jamie 02.8.28 2090
9  Concept2_1 Jamie 02.8.28 1969
8  Concept2 Jamie 02.8.28 2063
7  Concept1 Jamie 02.8.26 2281
6  Tri State Buffer Jamie 02.8.26 3562
5  8x3 Encoder Jamie 02.8.28 4180
4  3x8 Decoder Jamie 02.8.28 3855
3  4bit Comparator Jamie 02.8.26 3233
2  °¡À§ ¹ÙÀ§ º¸ °ÔÀÓ Jamie 02.8.26 5572
1  Two Input Logic Jamie 02.8.26 2477
[1]