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Concept2_1
# 9 Jamie    02.8.28 16:33

1.Spec

À̹ø¿¡ ºÐ¼®Çغ¼ ȸ·Î´Â concept2ÀÇ ÀÀ¿ëÀÔ´Ï´Ù.
concept2¿¡ con signalÀÌ 0ÀÏ ¶§¸¦ Á¤ÀÇÇÏÁö ¾Ê¾Ò´Âµ¥ À̰ÍÀÌ latch ¿ªÇÒÀ» ÇϰÔ
Çß½À´Ï´Ù.
¿©±â¼­´Â Ãâ·Â signal¿¡ °ªÀ» ÁöÁ¤ÇϹǷμ­ con signalÀÌ '0'ÀÏ ¶§ÀÇ Á¶°ÇÀ» ¸¸Á·ÇϰÔ
Çß½À´Ï´Ù.
Áï, if ~ else ~±¸¹®À» concept2_1°ú °°ÀÌ Ç¥ÇöÇß´Ù´Â °ÍÀ» ÀÌÇØÇÏ½Ã¸é µË´Ï´Ù.

2.Input/Output



3.Timing



4.Block Diagram



5.RTL Code : concept2_1.vhd
  Test Vector : concept2_1_tb.vhd

°Ô½Ã¹°: 96 °Ç, ÇöÀç: 1 / 1 ÂÊ
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98  interface JMJS 25.1.20 329
97  test plusargs value plusargs JMJS 24.9.5 348
96  color text JMJS 24.7.13 386
95  draw_hexa.v JMJS 10.6.17 2542
94  jmjsxram3.v JMJS 10.4.9 2438
93  Verilog document JMJS 11.1.24 3035
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2623
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4060
90  gtkwave PC version JMJS 09.3.30 2426
89  ncsim option example JMJS 08.12.1 4789
88  [¿µ»ó]keywords for web search JMJS 08.12.1 2387
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6546
86  ncverilog option example JMJS 10.6.8 8251
85  [Verilog]Latch example JMJS 08.12.1 2990
84  Pad verilog example JMJS 01.3.16 4925
83  [ModelSim] vector JMJS 01.3.16 2618
82  RTL Code ºÐ¼®¼ø¼­ JMJS 09.4.29 2866
81  [temp]PIPE JMJS 08.10.2 2261
80  [temp]always-forever ¹«ÇÑ·çÇÁ JMJS 08.10.2 2338
79  YCbCr2RGB.v JMJS 10.5.12 2533
78  [VHDL]rom64x8 JMJS 09.3.27 2081
77  [function]vector_compare JMJS 02.6.19 1983
76  [function]vector2integer JMJS 02.6.19 2185
75  [VHDL]ram8x4x8 JMJS 08.12.1 1923
74  [¿¹]shift JMJS 02.6.19 2375
73  test JMJS 09.7.20 2220
72  test JMJS 09.7.20 1791
71  test JMJS 09.7.20 1933
70  test JMJS 09.7.20 2026
69  test JMJS 09.7.20 2075
68  test JMJS 09.7.20 2009
67  test JMJS 09.7.20 1945
66  test JMJS 09.7.20 1891
65  test JMJS 09.7.20 2013
64  test JMJS 09.7.20 2206
63  test JMJS 09.7.20 2242
62  test JMJS 09.7.20 2134
61  VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§ JMJS 09.7.20 3929
60  test JMJS 09.7.20 1723
59  test JMJS 09.7.20 2063
58  test JMJS 09.7.20 1970
57  test JMJS 09.7.20 1940
56  test JMJS 09.7.20 1980
55  verilog Çаú »ùÇð­ÀÇ JMJS 16.5.30 2430
54  [verilog]create_generated_clock JMJS 15.4.28 2411
53  [Verilog]JDIFF JMJS 14.7.4 1803
52  [verilog]parameter definition JMJS 14.3.5 2087
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5026
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2686
49  Verdi JMJS 10.4.22 3569
48  draw hexa JMJS 10.4.9 2075
47  asfifo - Async FIFO JMJS 10.4.8 1936
46  VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡ JMJS 02.3.14 3613
45  synplify batch JMJS 10.3.8 2805
44  ÀüÀڽðè Type A JMJS 08.11.28 2296
43  I2C Webpage JMJS 08.2.25 2133
42  PC¿¡¼­ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog) JMJS 13.1.14 6241
41  [Verilog]vstring JMJS 17.9.27 2338
40  Riviera Simple Case JMJS 09.4.29 3432
39  [VHDL]DES Example JMJS 07.6.15 3287
38  [verilog]RAM example JMJS 09.6.5 3065
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2300
36  Jamie's VHDL Handbook JMJS 08.11.28 2991
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3572
34  RTL Job JMJS 09.4.29 2506
33  [VHDL]type example - package TYPES JMJS 06.2.2 1971
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9636
30  [verilog]array_module JMJS 05.12.8 2542
29  [verilog-2001]generate JMJS 05.12.8 3687
28  protected JMJS 05.11.18 2338
27  design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä? JMJS 09.7.20 3083
26  busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº? JMJS 04.11.9 2073
25  component¸¦ »ý¼ºÇؼ­ ´Ù¸¥ °÷¿¡¼­ È£ÃâÇÏ´Â ¹æ¹ý JMJS 04.11.4 2707
23  Array Of Array JMJS 04.8.16 2228
22  dumpfile, dumpvars JMJS 04.7.19 3923
21  Vending Machine Jamie 02.12.16 10360
20  Mini Vending Machine1 Jamie 02.12.10 7232
19  Mini Vending Machine Jamie 02.12.6 10066
18  Key Jamie 02.11.29 5263
17  Stop Watch Jamie 02.11.25 5813
16  Mealy Machine Jamie 02.8.29 6979
15  Moore Machine Jamie 02.8.29 18332
14  Up Down Counter Jamie 02.8.29 4350
13  Up Counter Jamie 02.8.29 3042
12  Edge Detecter Jamie 02.8.29 3258
11  Concept4 Jamie 02.8.28 2232
10  Concept3 Jamie 02.8.28 2324
9  Concept2_1 Jamie 02.8.28 2220
8  Concept2 Jamie 02.8.28 2305
7  Concept1 Jamie 02.8.26 2354
6  Tri State Buffer Jamie 02.8.26 3899
5  8x3 Encoder Jamie 02.8.28 4455
4  3x8 Decoder Jamie 02.8.28 4094
3  4bit Comparator Jamie 02.8.26 3474
2  °¡À§ ¹ÙÀ§ º¸ °ÔÀÓ Jamie 02.8.26 5647
1  Two Input Logic Jamie 02.8.26 2725
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