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Concept2_1
# 9 Jamie    02.8.28 16:33

1.Spec

이번에 분석해볼 회로는 concept2의 응용입니다.
concept2에 con signal이 0일 때를 정의하지 않았는데 이것이 latch 역할을 하게
했습니다.
여기서는 출력 signal에 값을 지정하므로서 con signal이 '0'일 때의 조건을 만족하게
했습니다.
즉, if ~ else ~구문을 concept2_1과 같이 표현했다는 것을 이해하시면 됩니다.

2.Input/Output



3.Timing



4.Block Diagram



5.RTL Code : concept2_1.vhd
  Test Vector : concept2_1_tb.vhd
게시물: 93 건, 현재: 1 / 1 쪽
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71  test JMJS 09.7.20 1313
70  test JMJS 09.7.20 1423
69  test JMJS 09.7.20 1450
68  test JMJS 09.7.20 1375
67  test JMJS 09.7.20 1296
66  test JMJS 09.7.20 1254
65  test JMJS 09.7.20 1362
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63  test JMJS 09.7.20 1610
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56  test JMJS 09.7.20 1383
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41  [Verilog]vstring JMJS 17.9.27 1776
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39  [VHDL]DES Example JMJS 07.6.15 2659
38  [verilog]RAM example JMJS 09.6.5 2436
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