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Concept2_1
# 9 Jamie    02.8.28 16:33

1.Spec

À̹ø¿¡ ºÐ¼®Çغ¼ ȸ·Î´Â concept2ÀÇ ÀÀ¿ëÀÔ´Ï´Ù.
concept2¿¡ con signalÀÌ 0ÀÏ ¶§¸¦ Á¤ÀÇÇÏÁö ¾Ê¾Ò´Âµ¥ À̰ÍÀÌ latch ¿ªÇÒÀ» ÇϰÔ
Çß½À´Ï´Ù.
¿©±â¼­´Â Ãâ·Â signal¿¡ °ªÀ» ÁöÁ¤ÇϹǷμ­ con signalÀÌ '0'ÀÏ ¶§ÀÇ Á¶°ÇÀ» ¸¸Á·ÇϰÔ
Çß½À´Ï´Ù.
Áï, if ~ else ~±¸¹®À» concept2_1°ú °°ÀÌ Ç¥ÇöÇß´Ù´Â °ÍÀ» ÀÌÇØÇÏ½Ã¸é µË´Ï´Ù.

2.Input/Output



3.Timing



4.Block Diagram



5.RTL Code : concept2_1.vhd
  Test Vector : concept2_1_tb.vhd

°Ô½Ã¹°: 96 °Ç, ÇöÀç: 1 / 1 ÂÊ
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98  interface JMJS 25.1.20 336
97  test plusargs value plusargs JMJS 24.9.5 350
96  color text JMJS 24.7.13 391
95  draw_hexa.v JMJS 10.6.17 2544
94  jmjsxram3.v JMJS 10.4.9 2459
93  Verilog document JMJS 11.1.24 3059
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2648
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4082
90  gtkwave PC version JMJS 09.3.30 2458
89  ncsim option example JMJS 08.12.1 4814
88  [¿µ»ó]keywords for web search JMJS 08.12.1 2420
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6550
86  ncverilog option example JMJS 10.6.8 8277
85  [Verilog]Latch example JMJS 08.12.1 3015
84  Pad verilog example JMJS 01.3.16 4959
83  [ModelSim] vector JMJS 01.3.16 2647
82  RTL Code ºÐ¼®¼ø¼­ JMJS 09.4.29 2879
81  [temp]PIPE JMJS 08.10.2 2289
80  [temp]always-forever ¹«ÇÑ·çÇÁ JMJS 08.10.2 2361
79  YCbCr2RGB.v JMJS 10.5.12 2554
78  [VHDL]rom64x8 JMJS 09.3.27 2106
77  [function]vector_compare JMJS 02.6.19 1993
76  [function]vector2integer JMJS 02.6.19 2210
75  [VHDL]ram8x4x8 JMJS 08.12.1 1931
74  [¿¹]shift JMJS 02.6.19 2394
73  test JMJS 09.7.20 2252
72  test JMJS 09.7.20 1792
71  test JMJS 09.7.20 1965
70  test JMJS 09.7.20 2054
69  test JMJS 09.7.20 2104
68  test JMJS 09.7.20 2043
67  test JMJS 09.7.20 1975
66  test JMJS 09.7.20 1917
65  test JMJS 09.7.20 2046
64  test JMJS 09.7.20 2233
63  test JMJS 09.7.20 2276
62  test JMJS 09.7.20 2162
61  VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§ JMJS 09.7.20 3952
60  test JMJS 09.7.20 1725
59  test JMJS 09.7.20 2094
58  test JMJS 09.7.20 1994
57  test JMJS 09.7.20 1967
56  test JMJS 09.7.20 2000
55  verilog Çаú »ùÇð­ÀÇ JMJS 16.5.30 2433
54  [verilog]create_generated_clock JMJS 15.4.28 2421
53  [Verilog]JDIFF JMJS 14.7.4 1839
52  [verilog]parameter definition JMJS 14.3.5 2114
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5053
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2695
49  Verdi JMJS 10.4.22 3602
48  draw hexa JMJS 10.4.9 2086
47  asfifo - Async FIFO JMJS 10.4.8 1947
46  VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡ JMJS 02.3.14 3627
45  synplify batch JMJS 10.3.8 2832
44  ÀüÀڽðè Type A JMJS 08.11.28 2326
43  I2C Webpage JMJS 08.2.25 2155
42  PC¿¡¼­ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog) JMJS 13.1.14 6245
41  [Verilog]vstring JMJS 17.9.27 2360
40  Riviera Simple Case JMJS 09.4.29 3444
39  [VHDL]DES Example JMJS 07.6.15 3320
38  [verilog]RAM example JMJS 09.6.5 3079
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2329
36  Jamie's VHDL Handbook JMJS 08.11.28 3025
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3602
34  RTL Job JMJS 09.4.29 2536
33  [VHDL]type example - package TYPES JMJS 06.2.2 1976
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9662
30  [verilog]array_module JMJS 05.12.8 2568
29  [verilog-2001]generate JMJS 05.12.8 3711
28  protected JMJS 05.11.18 2376
27  design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä? JMJS 09.7.20 3101
26  busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº? JMJS 04.11.9 2087
25  component¸¦ »ý¼ºÇؼ­ ´Ù¸¥ °÷¿¡¼­ È£ÃâÇÏ´Â ¹æ¹ý JMJS 04.11.4 2718
23  Array Of Array JMJS 04.8.16 2254
22  dumpfile, dumpvars JMJS 04.7.19 3958
21  Vending Machine Jamie 02.12.16 10392
20  Mini Vending Machine1 Jamie 02.12.10 7240
19  Mini Vending Machine Jamie 02.12.6 10080
18  Key Jamie 02.11.29 5294
17  Stop Watch Jamie 02.11.25 5821
16  Mealy Machine Jamie 02.8.29 7013
15  Moore Machine Jamie 02.8.29 18353
14  Up Down Counter Jamie 02.8.29 4376
13  Up Counter Jamie 02.8.29 3069
12  Edge Detecter Jamie 02.8.29 3290
11  Concept4 Jamie 02.8.28 2236
10  Concept3 Jamie 02.8.28 2350
9  Concept2_1 Jamie 02.8.28 2244
8  Concept2 Jamie 02.8.28 2333
7  Concept1 Jamie 02.8.26 2356
6  Tri State Buffer Jamie 02.8.26 3936
5  8x3 Encoder Jamie 02.8.28 4480
4  3x8 Decoder Jamie 02.8.28 4119
3  4bit Comparator Jamie 02.8.26 3490
2  °¡À§ ¹ÙÀ§ º¸ °ÔÀÓ Jamie 02.8.26 5649
1  Two Input Logic Jamie 02.8.26 2752
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