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synplify batch
# 45 JMJS    10.3.8 22:28

%cat run.tcl
project -load "proj_1.prj"
project -run synthesis
set_option -no_sequential_opt 1
%synplify_premier -help
%synplify_premier -batch run.tcl

게시물: 93 건, 현재: 1 / 1 쪽
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번호 제       목 작성자 등록일 방문
95  draw_hexa.v JMJS 10.6.17 2018
94  jmjsxram3.v JMJS 10.4.9 1763
93  Verilog document JMJS 11.1.24 2345
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 1917
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3401
90  gtkwave PC version JMJS 09.3.30 1711
89  ncsim option example JMJS 08.12.1 4098
88  [영상]keywords for web search JMJS 08.12.1 1732
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6064
86  ncverilog option example JMJS 10.6.8 7435
85  [Verilog]Latch example JMJS 08.12.1 2334
84  Pad verilog example JMJS 01.3.16 4256
83  [ModelSim] vector JMJS 01.3.16 1941
82  RTL Code 분석순서 JMJS 09.4.29 2231
81  [temp]PIPE JMJS 08.10.2 1600
80  [temp]always-forever 무한루프 JMJS 08.10.2 1668
79  YCbCr2RGB.v JMJS 10.5.12 1886
78  [VHDL]rom64x8 JMJS 09.3.27 1499
77  [function]vector_compare JMJS 02.6.19 1461
76  [function]vector2integer JMJS 02.6.19 1539
75  [VHDL]ram8x4x8 JMJS 08.12.1 1403
74  [예]shift JMJS 02.6.19 1767
73  test JMJS 09.7.20 1533
72  test JMJS 09.7.20 1343
71  test JMJS 09.7.20 1284
70  test JMJS 09.7.20 1389
69  test JMJS 09.7.20 1420
68  test JMJS 09.7.20 1346
67  test JMJS 09.7.20 1259
66  test JMJS 09.7.20 1225
65  test JMJS 09.7.20 1331
64  test JMJS 09.7.20 1598
63  test JMJS 09.7.20 1590
62  test JMJS 09.7.20 1522
61  VHDL의 연산자 우선순위 JMJS 09.7.20 3341
60  test JMJS 09.7.20 1254
59  test JMJS 09.7.20 1341
58  test JMJS 09.7.20 1369
57  test JMJS 09.7.20 1302
56  test JMJS 09.7.20 1345
55  verilog 학과 샘플강의 JMJS 16.5.30 1985
54  [verilog]create_generated_clock JMJS 15.4.28 1938
53  [Verilog]JDIFF JMJS 14.7.4 1220
52  [verilog]parameter definition JMJS 14.3.5 1477
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4406
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2206
49  Verdi JMJS 10.4.22 2790
48  draw hexa JMJS 10.4.9 1562
47  asfifo - Async FIFO JMJS 10.4.8 1396
46  VHDL을 이용한 회로설계의 장점 JMJS 02.3.14 3042
45  synplify batch JMJS 10.3.8 2147
44  전자시계 Type A JMJS 08.11.28 1647
43  I2C Webpage JMJS 08.2.25 1519
42  PC에서 간단히 Verilog 실행해보기 (Icarus Verilog) JMJS 13.1.14 5776
41  [Verilog]vstring JMJS 17.9.27 1751
40  Riviera Simple Case JMJS 09.4.29 2913
39  [VHDL]DES Example JMJS 07.6.15 2631
38  [verilog]RAM example JMJS 09.6.5 2426
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 1668
36  Jamie's VHDL Handbook JMJS 08.11.28 2319
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 2938
34  RTL Job JMJS 09.4.29 1797
33  [VHDL]type example - package TYPES JMJS 06.2.2 1483
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9150
30  [verilog]array_module JMJS 05.12.8 1865
29  [verilog-2001]generate JMJS 05.12.8 3071
28  protected JMJS 05.11.18 1685
27  design에 latch가 있으면 안되나요? JMJS 09.7.20 2523
26  bus의 데이타를 각 bit별로 출력하는 방법은? JMJS 04.11.9 1577
25  component를 생성해서 다른 곳에서 호출하는 방법 JMJS 04.11.4 2129
23  Array Of Array JMJS 04.8.16 1679
22  dumpfile, dumpvars JMJS 04.7.19 3318
21  Vending Machine Jamie 02.12.16 9809
20  Mini Vending Machine1 Jamie 02.12.10 6586
19  Mini Vending Machine Jamie 02.12.6 9471
18  Key Jamie 02.11.29 4672
17  Stop Watch Jamie 02.11.25 5389
16  Mealy Machine Jamie 02.8.29 6372
15  Moore Machine Jamie 02.8.29 16905
14  Up Down Counter Jamie 02.8.29 3673
13  Up Counter Jamie 02.8.29 2442
12  Edge Detecter Jamie 02.8.29 2657
11  Concept4 Jamie 02.8.28 1779
10  Concept3 Jamie 02.8.28 1739
9  Concept2_1 Jamie 02.8.28 1624
8  Concept2 Jamie 02.8.28 1700
7  Concept1 Jamie 02.8.26 1912
6  Tri State Buffer Jamie 02.8.26 3214
5  8x3 Encoder Jamie 02.8.28 3816
4  3x8 Decoder Jamie 02.8.28 3509
3  4bit Comparator Jamie 02.8.26 2870
2  가위 바위 보 게임 Jamie 02.8.26 5257
1  Two Input Logic Jamie 02.8.26 2141
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