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8x3 Encoder
# 5 Jamie    02.8.28 15:46

1.Spec

ÀÚ, ¿À´ÃÀº Encoder¿¡ ´ëÇØ ¾Ë¾Æº¸°Ú½À´Ï´Ù.
Encoder´Â º°°³ÀÇ data¸¦ codeedµÈ ÇüÅ·Π¹Ù²Ù±âÀ§ÇØ »ç¿ëµË´Ï´Ù.
½±°Ô ¼³¸íÇϸé 2**nÀÇ input lineÀ» °¡Áö°í ÀÖ´Â encoder´Â input data¸¦ encodeÇØ¼­
n encoded output lineÀ» ¸¸µé¾î ³À´Ï´Ù.
case¹®À» ÀÌ¿ëÇØ¼­ modelingÀ» Çϰí, default "don't care" value¸¦ »ç¿ëÇØ¾ßÇÕ´Ï´Ù.
±×·³, 8*3 encoder¸¦ designÇØ º¸°Ú½À´Ï´Ù.

2.Input/Output



3.RTL Code : encoder83.vhd
  Test Vector : encoder83_tb.vhd

°Ô½Ã¹°: 96 °Ç, ÇöÀç: 1 / 1 ÂÊ
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98  interface JMJS 25.1.20 340
97  test plusargs value plusargs JMJS 24.9.5 355
96  color text JMJS 24.7.13 400
95  draw_hexa.v JMJS 10.6.17 2553
94  jmjsxram3.v JMJS 10.4.9 2482
93  Verilog document JMJS 11.1.24 3075
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2668
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 4104
90  gtkwave PC version JMJS 09.3.30 2490
89  ncsim option example JMJS 08.12.1 4838
88  [¿µ»ó]keywords for web search JMJS 08.12.1 2448
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6559
86  ncverilog option example JMJS 10.6.8 8298
85  [Verilog]Latch example JMJS 08.12.1 3039
84  Pad verilog example JMJS 01.3.16 4988
83  [ModelSim] vector JMJS 01.3.16 2671
82  RTL Code ºÐ¼®¼ø¼­ JMJS 09.4.29 2907
81  [temp]PIPE JMJS 08.10.2 2312
80  [temp]always-forever ¹«ÇÑ·çÇÁ JMJS 08.10.2 2392
79  YCbCr2RGB.v JMJS 10.5.12 2575
78  [VHDL]rom64x8 JMJS 09.3.27 2120
77  [function]vector_compare JMJS 02.6.19 2002
76  [function]vector2integer JMJS 02.6.19 2235
75  [VHDL]ram8x4x8 JMJS 08.12.1 1947
74  [¿¹]shift JMJS 02.6.19 2419
73  test JMJS 09.7.20 2278
72  test JMJS 09.7.20 1801
71  test JMJS 09.7.20 1992
70  test JMJS 09.7.20 2079
69  test JMJS 09.7.20 2131
68  test JMJS 09.7.20 2072
67  test JMJS 09.7.20 2002
66  test JMJS 09.7.20 1944
65  test JMJS 09.7.20 2071
64  test JMJS 09.7.20 2258
63  test JMJS 09.7.20 2304
62  test JMJS 09.7.20 2184
61  VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§ JMJS 09.7.20 3966
60  test JMJS 09.7.20 1730
59  test JMJS 09.7.20 2114
58  test JMJS 09.7.20 2024
57  test JMJS 09.7.20 1987
56  test JMJS 09.7.20 2024
55  verilog Çаú »ùÇð­ÀÇ JMJS 16.5.30 2439
54  [verilog]create_generated_clock JMJS 15.4.28 2433
53  [Verilog]JDIFF JMJS 14.7.4 1867
52  [verilog]parameter definition JMJS 14.3.5 2134
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 5080
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2705
49  Verdi JMJS 10.4.22 3627
48  draw hexa JMJS 10.4.9 2096
47  asfifo - Async FIFO JMJS 10.4.8 1958
46  VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡ JMJS 02.3.14 3646
45  synplify batch JMJS 10.3.8 2852
44  ÀüÀڽðè Type A JMJS 08.11.28 2353
43  I2C Webpage JMJS 08.2.25 2178
42  PC¿¡¼­ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog) JMJS 13.1.14 6256
41  [Verilog]vstring JMJS 17.9.27 2373
40  Riviera Simple Case JMJS 09.4.29 3458
39  [VHDL]DES Example JMJS 07.6.15 3345
38  [verilog]RAM example JMJS 09.6.5 3106
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2351
36  Jamie's VHDL Handbook JMJS 08.11.28 3047
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3627
34  RTL Job JMJS 09.4.29 2563
33  [VHDL]type example - package TYPES JMJS 06.2.2 1988
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9682
30  [verilog]array_module JMJS 05.12.8 2588
29  [verilog-2001]generate JMJS 05.12.8 3734
28  protected JMJS 05.11.18 2403
27  design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä? JMJS 09.7.20 3118
26  busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº? JMJS 04.11.9 2097
25  component¸¦ »ý¼ºÇؼ­ ´Ù¸¥ °÷¿¡¼­ È£ÃâÇÏ´Â ¹æ¹ý JMJS 04.11.4 2732
23  Array Of Array JMJS 04.8.16 2273
22  dumpfile, dumpvars JMJS 04.7.19 3976
21  Vending Machine Jamie 02.12.16 10412
20  Mini Vending Machine1 Jamie 02.12.10 7263
19  Mini Vending Machine Jamie 02.12.6 10097
18  Key Jamie 02.11.29 5312
17  Stop Watch Jamie 02.11.25 5830
16  Mealy Machine Jamie 02.8.29 7039
15  Moore Machine Jamie 02.8.29 18373
14  Up Down Counter Jamie 02.8.29 4406
13  Up Counter Jamie 02.8.29 3100
12  Edge Detecter Jamie 02.8.29 3311
11  Concept4 Jamie 02.8.28 2243
10  Concept3 Jamie 02.8.28 2369
9  Concept2_1 Jamie 02.8.28 2266
8  Concept2 Jamie 02.8.28 2352
7  Concept1 Jamie 02.8.26 2361
6  Tri State Buffer Jamie 02.8.26 3961
5  8x3 Encoder Jamie 02.8.28 4504
4  3x8 Decoder Jamie 02.8.28 4138
3  4bit Comparator Jamie 02.8.26 3514
2  °¡À§ ¹ÙÀ§ º¸ °ÔÀÓ Jamie 02.8.26 5656
1  Two Input Logic Jamie 02.8.26 2774
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