LogIn E-mail
¼³°èÀ̾߱â
8x3 Encoder
# 5 Jamie    02.8.28 15:46

1.Spec

ÀÚ, ¿À´ÃÀº Encoder¿¡ ´ëÇØ ¾Ë¾Æº¸°Ú½À´Ï´Ù.
Encoder´Â º°°³ÀÇ data¸¦ codeedµÈ ÇüÅ·Π¹Ù²Ù±âÀ§ÇØ »ç¿ëµË´Ï´Ù.
½±°Ô ¼³¸íÇϸé 2**nÀÇ input lineÀ» °¡Áö°í ÀÖ´Â encoder´Â input data¸¦ encodeÇØ¼­
n encoded output lineÀ» ¸¸µé¾î ³À´Ï´Ù.
case¹®À» ÀÌ¿ëÇØ¼­ modelingÀ» Çϰí, default "don't care" value¸¦ »ç¿ëÇØ¾ßÇÕ´Ï´Ù.
±×·³, 8*3 encoder¸¦ designÇØ º¸°Ú½À´Ï´Ù.

2.Input/Output



3.RTL Code : encoder83.vhd
  Test Vector : encoder83_tb.vhd

°Ô½Ã¹°: 96 °Ç, ÇöÀç: 1 / 1 ÂÊ
¹øÈ£ Á¦       ¸ñ ÀÛ¼ºÀÚ µî·ÏÀÏ ¹æ¹®
98  interface JMJS 25.1.20 175
97  test plusargs value plusargs JMJS 24.9.5 243
96  color text JMJS 24.7.13 246
95  draw_hexa.v JMJS 10.6.17 2451
94  jmjsxram3.v JMJS 10.4.9 2177
93  Verilog document JMJS 11.1.24 2786
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2375
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3789
90  gtkwave PC version JMJS 09.3.30 2124
89  ncsim option example JMJS 08.12.1 4512
88  [¿µ»ó]keywords for web search JMJS 08.12.1 2146
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6453
86  ncverilog option example JMJS 10.6.8 7967
85  [Verilog]Latch example JMJS 08.12.1 2726
84  Pad verilog example JMJS 01.3.16 4655
83  [ModelSim] vector JMJS 01.3.16 2342
82  RTL Code ºÐ¼®¼ø¼­ JMJS 09.4.29 2626
81  [temp]PIPE JMJS 08.10.2 1993
80  [temp]always-forever ¹«ÇÑ·çÇÁ JMJS 08.10.2 2064
79  YCbCr2RGB.v JMJS 10.5.12 2298
78  [VHDL]rom64x8 JMJS 09.3.27 1881
77  [function]vector_compare JMJS 02.6.19 1829
76  [function]vector2integer JMJS 02.6.19 1921
75  [VHDL]ram8x4x8 JMJS 08.12.1 1794
74  [¿¹]shift JMJS 02.6.19 2158
73  test JMJS 09.7.20 1947
72  test JMJS 09.7.20 1720
71  test JMJS 09.7.20 1660
70  test JMJS 09.7.20 1758
69  test JMJS 09.7.20 1798
68  test JMJS 09.7.20 1740
67  test JMJS 09.7.20 1653
66  test JMJS 09.7.20 1630
65  test JMJS 09.7.20 1730
64  test JMJS 09.7.20 1951
63  test JMJS 09.7.20 1972
62  test JMJS 09.7.20 1873
61  VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§ JMJS 09.7.20 3686
60  test JMJS 09.7.20 1654
59  test JMJS 09.7.20 1756
58  test JMJS 09.7.20 1724
57  test JMJS 09.7.20 1684
56  test JMJS 09.7.20 1723
55  verilog Çаú »ùÇð­ÀÇ JMJS 16.5.30 2324
54  [verilog]create_generated_clock JMJS 15.4.28 2316
53  [Verilog]JDIFF JMJS 14.7.4 1580
52  [verilog]parameter definition JMJS 14.3.5 1850
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4807
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2579
49  Verdi JMJS 10.4.22 3297
48  draw hexa JMJS 10.4.9 1933
47  asfifo - Async FIFO JMJS 10.4.8 1776
46  VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡ JMJS 02.3.14 3411
45  synplify batch JMJS 10.3.8 2514
44  ÀüÀڽðè Type A JMJS 08.11.28 2028
43  I2C Webpage JMJS 08.2.25 1876
42  PC¿¡¼­ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog) JMJS 13.1.14 6037
41  [Verilog]vstring JMJS 17.9.27 2121
40  Riviera Simple Case JMJS 09.4.29 3248
39  [VHDL]DES Example JMJS 07.6.15 3010
38  [verilog]RAM example JMJS 09.6.5 2767
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2051
36  Jamie's VHDL Handbook JMJS 08.11.28 2726
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3349
34  RTL Job JMJS 09.4.29 2191
33  [VHDL]type example - package TYPES JMJS 06.2.2 1860
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9398
30  [verilog]array_module JMJS 05.12.8 2330
29  [verilog-2001]generate JMJS 05.12.8 3414
28  protected JMJS 05.11.18 2093
27  design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä? JMJS 09.7.20 2903
26  busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº? JMJS 04.11.9 1923
25  component¸¦ »ý¼ºÇؼ­ ´Ù¸¥ °÷¿¡¼­ È£ÃâÇÏ´Â ¹æ¹ý JMJS 04.11.4 2527
23  Array Of Array JMJS 04.8.16 2039
22  dumpfile, dumpvars JMJS 04.7.19 3642
21  Vending Machine Jamie 02.12.16 10116
20  Mini Vending Machine1 Jamie 02.12.10 6998
19  Mini Vending Machine Jamie 02.12.6 9851
18  Key Jamie 02.11.29 5014
17  Stop Watch Jamie 02.11.25 5704
16  Mealy Machine Jamie 02.8.29 6772
15  Moore Machine Jamie 02.8.29 18000
14  Up Down Counter Jamie 02.8.29 4106
13  Up Counter Jamie 02.8.29 2805
12  Edge Detecter Jamie 02.8.29 3015
11  Concept4 Jamie 02.8.28 2135
10  Concept3 Jamie 02.8.28 2102
9  Concept2_1 Jamie 02.8.28 1987
8  Concept2 Jamie 02.8.28 2078
7  Concept1 Jamie 02.8.26 2288
6  Tri State Buffer Jamie 02.8.26 3577
5  8x3 Encoder Jamie 02.8.28 4198
4  3x8 Decoder Jamie 02.8.28 3863
3  4bit Comparator Jamie 02.8.26 3241
2  °¡À§ ¹ÙÀ§ º¸ °ÔÀÓ Jamie 02.8.26 5579
1  Two Input Logic Jamie 02.8.26 2485
[1]