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ncverilog option example
# 86 JMJS    10.6.8 00:08

ncverilog \
        +access+rwc \
        +ncloadpli1=debpli:deb_PLIPtr \
        +libexe+.mdlp+.v+liborder_libverbose \
        +licq \
        +maxdelays \        #or +mindelays for GATE sim
        +no_notifier \
        +nowarn+MGWARNING \
        +nowarn+WARNING \
        +notchkmsg \
        +define+functional_mode \ #for RTL sim
        +define+NO_MEM_MESSAGES \
        +incdir+/.../INC  \
         +nctimescale+1ns/10ps \
        -f ../local.f \
        ./top.v \
        -l ./log/abc.log

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98  interface JMJS 25.1.20 183
97  test plusargs value plusargs JMJS 24.9.5 251
96  color text JMJS 24.7.13 254
95  draw_hexa.v JMJS 10.6.17 2458
94  jmjsxram3.v JMJS 10.4.9 2190
93  Verilog document JMJS 11.1.24 2799
92  [verilog]o=(c1)? (c2)? 0:1 : (c3)? 2:3; JMJS 09.3.31 2384
91  [verilog]forever, repeat, strobe, realtime, ... JMJS 09.7.6 3801
90  gtkwave PC version JMJS 09.3.30 2139
89  ncsim option example JMJS 08.12.1 4521
88  [¿µ»ó]keywords for web search JMJS 08.12.1 2154
87  [Verilog]fdisplay fopen fscanf JMJS 11.1.24 6459
86  ncverilog option example JMJS 10.6.8 7996
85  [Verilog]Latch example JMJS 08.12.1 2736
84  Pad verilog example JMJS 01.3.16 4665
83  [ModelSim] vector JMJS 01.3.16 2355
82  RTL Code ºÐ¼®¼ø¼­ JMJS 09.4.29 2639
81  [temp]PIPE JMJS 08.10.2 2002
80  [temp]always-forever ¹«ÇÑ·çÇÁ JMJS 08.10.2 2082
79  YCbCr2RGB.v JMJS 10.5.12 2309
78  [VHDL]rom64x8 JMJS 09.3.27 1889
77  [function]vector_compare JMJS 02.6.19 1833
76  [function]vector2integer JMJS 02.6.19 1932
75  [VHDL]ram8x4x8 JMJS 08.12.1 1800
74  [¿¹]shift JMJS 02.6.19 2168
73  test JMJS 09.7.20 1955
72  test JMJS 09.7.20 1726
71  test JMJS 09.7.20 1673
70  test JMJS 09.7.20 1769
69  test JMJS 09.7.20 1810
68  test JMJS 09.7.20 1757
67  test JMJS 09.7.20 1668
66  test JMJS 09.7.20 1644
65  test JMJS 09.7.20 1748
64  test JMJS 09.7.20 1961
63  test JMJS 09.7.20 1984
62  test JMJS 09.7.20 1890
61  VHDLÀÇ ¿¬»êÀÚ ¿ì¼±¼øÀ§ JMJS 09.7.20 3693
60  test JMJS 09.7.20 1660
59  test JMJS 09.7.20 1770
58  test JMJS 09.7.20 1733
57  test JMJS 09.7.20 1698
56  test JMJS 09.7.20 1737
55  verilog Çаú »ùÇð­ÀÇ JMJS 16.5.30 2331
54  [verilog]create_generated_clock JMJS 15.4.28 2320
53  [Verilog]JDIFF JMJS 14.7.4 1585
52  [verilog]parameter definition JMJS 14.3.5 1859
51  [verilog]sformat fopen fscanf fwrite fclose JMJS 12.1.31 4812
50  Verilog File I/0,Verilog file handling JMJS 12.1.30 2584
49  Verdi JMJS 10.4.22 3306
48  draw hexa JMJS 10.4.9 1938
47  asfifo - Async FIFO JMJS 10.4.8 1785
46  VHDLÀ» ÀÌ¿ëÇÑ È¸·Î¼³°èÀÇ ÀåÁ¡ JMJS 02.3.14 3422
45  synplify batch JMJS 10.3.8 2531
44  ÀüÀڽðè Type A JMJS 08.11.28 2046
43  I2C Webpage JMJS 08.2.25 1892
42  PC¿¡¼­ °£´ÜÈ÷ Verilog ½ÇÇàÇØº¸±â (Icarus Verilog) JMJS 13.1.14 6044
41  [Verilog]vstring JMJS 17.9.27 2129
40  Riviera Simple Case JMJS 09.4.29 3259
39  [VHDL]DES Example JMJS 07.6.15 3020
38  [verilog]RAM example JMJS 09.6.5 2786
37  ROM example [VerilogHDL, RTL] JMJS 04.5.27 2069
36  Jamie's VHDL Handbook JMJS 08.11.28 2736
35  Dualport RAM example [VerilogHDL, RTL] JMJS 04.5.27 3363
34  RTL Job JMJS 09.4.29 2203
33  [VHDL]type example - package TYPES JMJS 06.2.2 1866
32  [verilog]`define `ifdef `elsif `else `endif ... JMJS 10.5.11 9407
30  [verilog]array_module JMJS 05.12.8 2344
29  [verilog-2001]generate JMJS 05.12.8 3426
28  protected JMJS 05.11.18 2104
27  design¿¡ latch°¡ ÀÖÀ¸¸é ¾ÈµÇ³ª¿ä? JMJS 09.7.20 2917
26  busÀÇ µ¥ÀÌŸ¸¦ °¢ bitº°·Î Ãâ·ÂÇÏ´Â ¹æ¹ýÀº? JMJS 04.11.9 1927
25  component¸¦ »ý¼ºÇؼ­ ´Ù¸¥ °÷¿¡¼­ È£ÃâÇÏ´Â ¹æ¹ý JMJS 04.11.4 2535
23  Array Of Array JMJS 04.8.16 2047
22  dumpfile, dumpvars JMJS 04.7.19 3658
21  Vending Machine Jamie 02.12.16 10124
20  Mini Vending Machine1 Jamie 02.12.10 7009
19  Mini Vending Machine Jamie 02.12.6 9862
18  Key Jamie 02.11.29 5024
17  Stop Watch Jamie 02.11.25 5708
16  Mealy Machine Jamie 02.8.29 6782
15  Moore Machine Jamie 02.8.29 18017
14  Up Down Counter Jamie 02.8.29 4118
13  Up Counter Jamie 02.8.29 2816
12  Edge Detecter Jamie 02.8.29 3032
11  Concept4 Jamie 02.8.28 2139
10  Concept3 Jamie 02.8.28 2118
9  Concept2_1 Jamie 02.8.28 2002
8  Concept2 Jamie 02.8.28 2094
7  Concept1 Jamie 02.8.26 2293
6  Tri State Buffer Jamie 02.8.26 3594
5  8x3 Encoder Jamie 02.8.28 4217
4  3x8 Decoder Jamie 02.8.28 3878
3  4bit Comparator Jamie 02.8.26 3257
2  °¡À§ ¹ÙÀ§ º¸ °ÔÀÓ Jamie 02.8.26 5583
1  Two Input Logic Jamie 02.8.26 2499
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